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* lm386 subcircuit model follows:
************************************original* IC pins: 2 3 7 1 8 5 6 4
* IC pins: 1 2 3 4 5 6 7 8
* | | | | | | | |
.subckt lm386 g1 inn inp gnd out vs byp g8
************************************original*.subckt lm386 inn inp byp g1 g8 out vs gnd
* input emitter-follower buffers:
q1 gnd inn 10011 ddpnp
r1 inn gnd 50k
q2 gnd inp 10012 ddpnp
r2 inp gnd 50k
* differential input stage, gain-setting
* resistors, and internal feedback resistor:
q3 10013 10011 10008 ddpnp
q4 10014 10012 g1 ddpnp
r3 vs byp 15k
r4 byp 10008 15k
r5 10008 g8 150
r6 g8 g1 1.35k
r7 g1 out 15k
* input stage current mirror:
q5 10013 10013 gnd ddnpn
q6 10014 10013 gnd ddnpn
* voltage gain stage & rolloff cap:
q7 10017 10014 gnd ddnpn
c1 10014 10017 15pf
* current mirror source for gain stage:
i1 10002 vs dc 5m
q8 10004 10002 vs ddpnp
q9 10002 10002 vs ddpnp
* Sziklai-connected push-pull output stage:
q10 10018 10017 out ddpnp
q11 10004 10004 10009 ddnpn 100
q12 10009 10009 10017 ddnpn 100
q13 vs 10004 out ddnpn 100
q14 out 10018 gnd ddnpn 100
* generic transistor models generated
* with MicroSim's PARTs utility, using
* default parameters except Bf:
.model ddnpn NPN(Is=10f Xti=3 Eg=1.11 Vaf=100
+ Bf=400 Ise=0 Ne=1.5 Ikf=0 Nk=.5 Xtb=1.5 Var=100
+ Br=1 Isc=0 Nc=2 Ikr=0 Rc=0 Cjc=2p Mjc=.3333
+ Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n
+ Tf=1n Itf=1 Xtf=0 Vtf=10)
.model ddpnp PNP(Is=10f Xti=3 Eg=1.11 Vaf=100
+ Bf=200 Ise=0 Ne=1.5 Ikf=0 Nk=.5 Xtb=1.5 Var=100
+ Br=1 Isc=0 Nc=2 Ikr=0 Rc=0 Cjc=2p Mjc=.3333
+ Vjc=.75 Fc=.5 Cje=5p Mje=.3333 Vje=.75 Tr=10n
+ Tf=1n Itf=1 Xtf=0 Vtf=10)
.ends
*----------end of subcircuit model-----------
habbott said:Hi , thanks for the help but I am new to this. Has anyone got a complete model ready to go so I can just us it in my software program
Version 4
SymbolType CELL
LINE Normal -64 -63 64 0
LINE Normal -64 65 64 0
LINE Normal -64 -63 -64 65
LINE Normal -60 -48 -52 -48
LINE Normal -60 48 -52 48
LINE Normal -56 52 -56 44
LINE Normal -48 -80 -48 -55
LINE Normal -48 80 -48 57
LINE Normal -44 -68 -36 -68
LINE Normal -40 -72 -40 -64
LINE Normal -44 68 -36 68
LINE Normal -16 -39 -16 -64
LINE Normal 0 32 0 48
LINE Normal 48 -8 48 -32
TEXT -51 1 Left 0 LM386
SYMATTR Prefix X
SYMATTR Description Low power audio amplifier
SYMATTR ModelFile LM386.sub
SYMATTR SpiceModel LM386.sub
PIN -16 -64 LEFT 8
PINATTR PinName g1
PINATTR SpiceOrder 1
PIN -64 -48 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN -64 48 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 3
PIN -48 80 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 64 0 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5
PIN -48 -80 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 6
PIN 0 48 LEFT 8
PINATTR PinName bp
PINATTR SpiceOrder 7
PIN 48 -32 LEFT 8
PINATTR PinName g8
PINATTR SpiceOrder 8
Version 4
SymbolType CELL
LINE Normal -64 -63 64 0
LINE Normal -64 65 64 0
LINE Normal -64 -63 -64 65
LINE Normal -60 -48 -52 -48
LINE Normal -60 48 -52 48
LINE Normal -56 52 -56 44
LINE Normal -48 -80 -48 -55
LINE Normal -48 80 -48 57
LINE Normal -44 -68 -36 -68
LINE Normal -40 -72 -40 -64
LINE Normal -44 68 -36 68
LINE Normal -16 -39 -16 -64
LINE Normal 0 32 0 48
LINE Normal 48 -8 48 -32
SYMATTR Value LM386
SYMATTR Prefix X
SYMATTR ModelFile LM386.sub
SYMATTR Value2 LM386
SYMATTR Description Low power audio amplifier
PIN -16 -64 LEFT 8
PINATTR PinName g1
PINATTR SpiceOrder 1
PIN -64 -48 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN -64 48 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 3
PIN -48 80 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 64 0 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5
PIN -48 -80 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 6
PIN 0 48 LEFT 8
PINATTR PinName bp
PINATTR SpiceOrder 7
PIN 48 -32 LEFT 8
PINATTR PinName g8
PINATTR SpiceOrder 8
Compare the file I gave you with the file you posted. I took yours and edited it until it looked like LM555.asy.Thanks Roff.
Do you know where I had gone wrong (apart from not including a value for C4 which shouldn't have given me that error)?
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
* ///////////////////////////////////////////////////////////////////
* User Notes:
*
* 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is
* modeled by assuming the option GMIN=1TOhm. If a different (non-
* default) GMIN value is needed, users may recalculate as follows:
* Rin=(R1||GMIN+R2||GMIN), where R1=R2,
* to maintain a consistent Rin model.
*//////////////////////////////////////////////////////////
*LF412 LOW OFFSET, LOW DRIFT DUAL JFET INPUT OP-AMP MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LF412/NS 1 2 99 50 28
*
*Features:
*Fast settling time (.01%) = 2uS
*High bandwidth = 3MHz
*High slew rate = 10V/uS
*Low offset voltage = 1mV
*Low supply current = 1.8mA
*NOTE: Model is for single device only and simulated
* supply current is 1/2 of total device current.
*
****************INPUT STAGE**************
*
IOS 2 1 25.0P
*^Input offset current
CI1 1 0 3P
CI2 2 0 3P
R1 1 3 1E12
R2 3 2 1E12
I1 99 4 1.0M
J1 5 2 4 JX
J2 6 7 4 JX
R3 5 50 650
R4 6 50 650
*Fp2=28 MHZ
C4 5 6 4.372P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 800UA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 1E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 2.13
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.13
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 5 6 20E-3
R5 98 9 10MEG
VA3 9 11 0
*Fp1=18 HZ
C3 98 11 857.516P
*
***************POLE STAGE***************
*
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.305E-15
*
*********COMMON-MODE ZERO STAGE*********
*
G4 98 16 3 49 1E-8
L2 98 17 144.7M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 15 1
VA8 26 27 0
R16 27 28 50
V5 28 25 0.646V
D4 25 15 DX
V4 24 28 0.646V
D3 15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.183E-3 VTO=-.65 IS=50E-12)
*
.ENDS
*$
Version 4
SymbolType CELL
LINE Normal -32 32 32 64
LINE Normal -32 96 32 64
LINE Normal -32 32 -32 96
LINE Normal -28 48 -20 48
LINE Normal -28 80 -20 80
LINE Normal -24 84 -24 76
LINE Normal 0 32 0 48
LINE Normal 0 96 0 80
LINE Normal 4 44 12 44
LINE Normal 8 40 8 48
LINE Normal 4 84 12 84
WINDOW 0 16 32 Left 0
WINDOW 3 16 96 Left 0
SYMATTR Value LF412
SYMATTR Prefix X
SYMATTR ModelFile LF412.sub
SYMATTR Value2 LF412
SYMATTR Description LF412 Low offset, low drift dual JFET input Op-Amp
PIN -32 80 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -32 48 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 0 32 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 0 96 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 32 64 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5
If you don't know how to connect the model, that's a different problem but the model is as complete as it'll ever be.
This seems to work:
You can also do it as in the attached file if you don't want to create a symbol. The 8 pin symbol is in the Misc library.Code:Version 4 SymbolType CELL LINE Normal -64 -63 64 0 LINE Normal -64 65 64 0 LINE Normal -64 -63 -64 65 LINE Normal -60 -48 -52 -48 LINE Normal -60 48 -52 48 LINE Normal -56 52 -56 44 LINE Normal -48 -80 -48 -55 LINE Normal -48 80 -48 57 LINE Normal -44 -68 -36 -68 LINE Normal -40 -72 -40 -64 LINE Normal -44 68 -36 68 LINE Normal -16 -39 -16 -64 LINE Normal 0 32 0 48 LINE Normal 48 -8 48 -32 SYMATTR Value LM386 SYMATTR Prefix X SYMATTR ModelFile LM386.sub SYMATTR Value2 LM386 SYMATTR Description Low power audio amplifier PIN -16 -64 LEFT 8 PINATTR PinName g1 PINATTR SpiceOrder 1 PIN -64 -48 NONE 0 PINATTR PinName In- PINATTR SpiceOrder 2 PIN -64 48 NONE 0 PINATTR PinName In+ PINATTR SpiceOrder 3 PIN -48 80 NONE 0 PINATTR PinName V- PINATTR SpiceOrder 4 PIN 64 0 NONE 0 PINATTR PinName OUT PINATTR SpiceOrder 5 PIN -48 -80 NONE 0 PINATTR PinName V+ PINATTR SpiceOrder 6 PIN 0 48 LEFT 8 PINATTR PinName bp PINATTR SpiceOrder 7 PIN 48 -32 LEFT 8 PINATTR PinName g8 PINATTR SpiceOrder 8