A missing pulse detector circuit (watchdog timer) is often used to determine if a system is properly operating.
Shown here are three circuits to perform that function.
All the circuits give a high output when the pulses stop, independent of the input pulse DC voltage at that point.
Not all missing pulse circuits are insensitive to the input DC level, but that's important, since the pulse input could arbitrarily stop either high or low if there's a problem with the system.
Here is the LTspice simulation of a missing pulse circuit using the LM339/393 comparator IC.
U1 discharges C1 (red trace) at the positive edge of each clock pulse (blue trace), keeping it below the Ref voltage of U2, so its Out (yellow trace) signal remains low.
When the input pulses stops, C1 will then charge and exceed the Ref voltage after approximately one R1C1 time-constant, at which point Out goes high.
R1 and C1 can be changed to give the desired delay for Out to go high after the pulses stop.
Typically this is made somewhat longer than one pulse period.
The delay for output turn-on is largely insensitive to supply voltage, staying close to one R1C1 time-constant.
----------------------------------------------------------------------------------------------
Below it the LTspice simulation of a missing pulse circuit using a CD4093 CMOS Schmitt trigger NAND gate package (a CD40106 Schmitt trigger inverter can also be used).
It's operation is similar to the LM339/393 circuit.
U1 charges C1 through D1 at the falling edge of each clock pulse, keeping its voltage above the logic threshold of U4 and thus the Out voltage low.
When the input pulses stops, U1's output will go low due to the bias from R2 and R3, causing C1 to discharge and go below U4's threshold voltage after approximately one R1C1 time-constant from the last input pulse trailing edge, at which point Out goes high.
R1 and C2 can be changed to give the desired delay for Out to go high after the pulses stop.
Typically this is made somewhat longer than one pulse period.
The delay for output turn-on is fairly insensitive to supply voltage, staying close to one R1C1 time-constant.
Its delay is not quite a stable as the LM339/393 circuit from temperature and voltage changes but should be adequate for most applications.
----------------------------------------------------------------------------------------------------------
Below is the LTspice simulation of a missing pulse detector circuit using a 555 timer IC.
The 555 basically functions here as a Set/Reset flip-flop controlled by the TRIG (/Set) and THRS (Reset) inputs.
With no input pulses, the Trig voltage is low, causing the output voltage to be high.
An input pulse momentarily turns on Q1 at the pulse's falling edge, charging C1 to near V+. This is above the THRS trigger voltage (about 2/3 V+), resetting the 555 Output to zero.
As long as pulses continue before C1 discharges below the TRIG trigger voltage (about 1/3 V+), the Output stays low.
An interruption in pulses allows C1 to discharge through R1 to below the TRIG trip point, setting the Output to high about 1.3 R1C1 time-constant after the falling edge of the last pulse. (The R1C1 time-constant can be changed, of course, to give the desired delay before the Output goes high after the last pulse ).
The output then stays high until it receives another input pulse.
Shown here are three circuits to perform that function.
All the circuits give a high output when the pulses stop, independent of the input pulse DC voltage at that point.
Not all missing pulse circuits are insensitive to the input DC level, but that's important, since the pulse input could arbitrarily stop either high or low if there's a problem with the system.
Here is the LTspice simulation of a missing pulse circuit using the LM339/393 comparator IC.
U1 discharges C1 (red trace) at the positive edge of each clock pulse (blue trace), keeping it below the Ref voltage of U2, so its Out (yellow trace) signal remains low.
When the input pulses stops, C1 will then charge and exceed the Ref voltage after approximately one R1C1 time-constant, at which point Out goes high.
R1 and C1 can be changed to give the desired delay for Out to go high after the pulses stop.
Typically this is made somewhat longer than one pulse period.
The delay for output turn-on is largely insensitive to supply voltage, staying close to one R1C1 time-constant.
----------------------------------------------------------------------------------------------
Below it the LTspice simulation of a missing pulse circuit using a CD4093 CMOS Schmitt trigger NAND gate package (a CD40106 Schmitt trigger inverter can also be used).
It's operation is similar to the LM339/393 circuit.
U1 charges C1 through D1 at the falling edge of each clock pulse, keeping its voltage above the logic threshold of U4 and thus the Out voltage low.
When the input pulses stops, U1's output will go low due to the bias from R2 and R3, causing C1 to discharge and go below U4's threshold voltage after approximately one R1C1 time-constant from the last input pulse trailing edge, at which point Out goes high.
R1 and C2 can be changed to give the desired delay for Out to go high after the pulses stop.
Typically this is made somewhat longer than one pulse period.
The delay for output turn-on is fairly insensitive to supply voltage, staying close to one R1C1 time-constant.
Its delay is not quite a stable as the LM339/393 circuit from temperature and voltage changes but should be adequate for most applications.
----------------------------------------------------------------------------------------------------------
Below is the LTspice simulation of a missing pulse detector circuit using a 555 timer IC.
The 555 basically functions here as a Set/Reset flip-flop controlled by the TRIG (/Set) and THRS (Reset) inputs.
With no input pulses, the Trig voltage is low, causing the output voltage to be high.
An input pulse momentarily turns on Q1 at the pulse's falling edge, charging C1 to near V+. This is above the THRS trigger voltage (about 2/3 V+), resetting the 555 Output to zero.
As long as pulses continue before C1 discharges below the TRIG trigger voltage (about 1/3 V+), the Output stays low.
An interruption in pulses allows C1 to discharge through R1 to below the TRIG trip point, setting the Output to high about 1.3 R1C1 time-constant after the falling edge of the last pulse. (The R1C1 time-constant can be changed, of course, to give the desired delay before the Output goes high after the last pulse ).
The output then stays high until it receives another input pulse.
