project10 Project Status | |||
Project File: | project10.ise | Current State: | Programming File Generated |
Module Name: | mainIncrementer |
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No Errors |
Target Device: | xc3s100e-5tq144 |
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10 Warnings |
Product Version: | ISE 10.1 - WebPACK |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Timing Report) |
project10 Partition Summary | [-] | |||
No partition information was found. |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 39 | 1,920 | 2% | ||
Number of 4 input LUTs | 58 | 1,920 | 3% | ||
Logic Distribution | |||||
Number of occupied Slices | 44 | 960 | 4% | ||
Number of Slices containing only related logic | 44 | 44 | 100% | ||
Number of Slices containing unrelated logic | 0 | 44 | 0% | ||
Total Number of 4 input LUTs | 75 | 1,920 | 3% | ||
Number used as logic | 58 | ||||
Number used as a route-thru | 17 | ||||
Number of bonded IOBs | 17 | 108 | 15% | ||
Number of BUFGMUXs | 1 | 24 | 4% |
Performance Summary | [-] | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri May 1 18:59:46 2009 | 0 | 4 Warnings | 1 Info | |
Translation Report | Current | Fri May 1 18:59:54 2009 | 0 | 0 | 0 | |
Map Report | Current | Fri May 1 19:00:00 2009 | 0 | 2 Warnings | 2 Infos | |
Place and Route Report | Current | Fri May 1 19:00:08 2009 | 0 | 4 Warnings | 2 Infos | |
Static Timing Report | Current | Fri May 1 19:00:11 2009 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Fri May 1 19:00:15 2009 | 0 | 0 | 0 |