project10 Project Status
Project File: project10.ise Current State: Programming File Generated
Module Name: mainIncrementer
  • Errors:
No Errors
Target Device: xc3s100e-5tq144
  • Warnings:
10 Warnings
Product Version: ISE 10.1 - WebPACK
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
project10 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 39 1,920 2%  
Number of 4 input LUTs 58 1,920 3%  
Logic Distribution     
Number of occupied Slices 44 960 4%  
    Number of Slices containing only related logic 44 44 100%  
    Number of Slices containing unrelated logic 0 44 0%  
Total Number of 4 input LUTs 75 1,920 3%  
    Number used as logic 58      
    Number used as a route-thru 17      
Number of bonded IOBs 17 108 15%  
Number of BUFGMUXs 1 24 4%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri May 1 18:59:46 200904 Warnings1 Info
Translation ReportCurrentFri May 1 18:59:54 2009000
Map ReportCurrentFri May 1 19:00:00 200902 Warnings2 Infos
Place and Route ReportCurrentFri May 1 19:00:08 200904 Warnings2 Infos
Static Timing ReportCurrentFri May 1 19:00:11 2009003 Infos
Bitgen ReportCurrentFri May 1 19:00:15 2009000

Date Generated: 05/01/2009 - 19:33:06