Building a DRSSTC Pt. 15 - The Interrupter (Pt. 2)

Hello everyone. Unfortunately my last entry didn't all fit in one post, so I had to split it up. Here is the rest of the Interrupter design explanation.

Pulse Width

96473

This part of the circuit is where we create the adjustment for the pulse width (duty cycle). As mentioned in the previous section, we do not take our frequency from the output pin of the 555 timer, but instead we take it from the trigger pin. In case you are not familiar with the operation of a 555 timer, here is the internal schematic:



The three resistors in series between Vcc and GND (R3, R4, and R5 in the above circuit) form a voltage divider with two taps, one at 1/3 of Vcc and one at 2/3 of Vcc. These form the voltage references for two comparators (C1 and C2 in the above circuit), which also have as their other inputs Threshhold and Trigger, respectively. The outputs of these comparators are then fed into a flip-flop, which sets the output of the 555 timer based on the state of the comparator outputs.

During normal operation, the capacitor voltage can be assumed to start at 0 volts. When a voltage is applied, it begins charging through R1 and R2 (the external resistors). At the exact point where the voltage on the capacitor exceeds 2/3 of Vcc, the upper comparator switches on (since the non-inverting input is higher than the inverting input), which resets the flip-flop. This means that is high, which switches on the transistor (Q14 in the above schematic), which then begins to discharge the capacitor. When the capacitor voltage drops just below 1/3 of Vcc, the lower comparator switches on which sets the flip-flop, thus turning off the transistor. The capacitor begins to charge once more and the cycle repeats.

Based on this circuit and description, you may begin to see that the signal on the trigger pin is actually a sawtooth-like wave that shows the charge and discharge curves of the capacitor, with an upper voltage of 2/3 Vcc and a lower voltage of 1/3 Vcc. It looks something like this:

96474

So here's the fun part: Somehow we need to take that waveform, turn it into a square wave, and be able to adjust the duty cycle. Thankfully this is quite easy to do with another comparator and an adjustable voltage reference. By feeding the sawtooth signal into one of the inputs of the comparator, and a voltage from a voltage divider made up of three resistors (two outer ones are fixed 10k and the middle one is a 10k pot), it is possible to adjust the reference voltage between 1/3 Vcc and 2/3 Vcc to match the input waveform. Since a comparator turns on the output if the voltage on the non-inverting input is higher than the voltage on the inverting input, adjusting the potentiometer in the voltage divider will adjust at which point the comparator switches the output on or off.

I realize this is probably very difficult to understand just by reading, so here is an animated GIF I created to demonstrate:

96475

The green waveform is the output from the comparator. As you can see, adjusting the voltage reference changes where the comparator switches, and thus changes the pulse width/duty cycle.

Now that's all fine and dandy, but what about the duty cycle limit? Well, that's also pretty easy. Remember how we were going to use a voltage divider made up of three resistors (two fixed, one adjustable) between Vcc and GND, allowing us to adjust the voltage reference between 1/3 Vcc and 2/3 Vcc? Well, what we actually need to do, since the minimum duty cycle is when the voltage reference is at its highest, in order to set the maximum duty cycle we need to set a lower voltage limit. This can be done by using another voltage divider with a potentiometer to set the voltage (R7, R9, and R11), and a voltage follower op-amp (U2A) to supply a voltage to replace GND in the duty cycle adjustment divider (R5 and R8). This means that the duty cycle potentiometer (R8) will adjust between the set voltage and 5V, thus limiting the pulse width to that range. A 5k resistor was selected for R5 to ensure that the maximum reference voltage matches that of the peak of the trigger waveform, at 2/3 Vcc. This can be proven using the voltage divider formula, assuming R8 is at its highest resistance (10k):



The voltage follower is only used to decouple the two resistor divider networks. If the first divider fed directly into the second, the divider ratios would be different and the max pulse width and duty cycle adjustments would not be independent.

The voltage reference is finally fed into U2B and U2C from the divider made up of R5 and R8 which is set up as a comparator. This is what converts our trigger signal into a square wave with an adjustable duty cycle. U2C provides us with a non-inverted version of our duty cycle that can be probed using TP3, and that is fed into a diode AND gate later on. U2B is also wired as a comparator (like U2C), but unlike U2C its inputs are swapped. This inverts the output that triggers U3, since the trigger input on a 555 is active-low. More on this in the next section.

On-Time

96476

This part of the circuit allows the operator to set a maximum on-time for each pulse. This is done rather crudely by a 555-timer in monostable mode. In general, monostable 555 timers cannot be trusted to deliver an accurate pulse of less than 10uS. The circuit shown above has a theoretical on-time adjustment available between 0S and about 500uS (517uS to be more precise). I will be testing this on the scope before hooking up my coil to see how low I can go. I am shooting for an on-time of around 10uS, so I would certainly be pushing the coil to its limits. The longer it's on, the longer the transistors will be on, and the hotter they'll get due to the high currents flowing through them. With sufficient cooling, a higher on-time may be permissible.

As you can see, this 555 timer is triggered by the output from U2B, which is our inverted duty cycle signal. This way we ensure that the timer starts counting as soon as the actual duty cycle (non-inverted) switches high.

Remember, according to criteria #5 the final output signal must have a pulse width matching the pulse width set by R8, or a pulse width matching the maximum on-time set by R3, whichever is shorter. In order to do this we need to make a sort of AND gate. The output can only be HIGH when BOTH inputs are high. This ensures that it turns off if either of the signals (the main signal with adjusted duty cycle or the timing signal from U3) turn off. This is how we make sure that the output abides by the limits set by the operator. The most basic analog AND gate uses two diodes. The anodes are connected together and to Vcc. The cathode of one is connected to one of the signals and the cathode of the other is connected to the other signal. In my case, D1 is connected to the timing output and D2 is connected to the main signal output. When both signals are high, no current flows through the diodes because there (theoretically) is no potential difference (both cathodes are at Vcc, as are both anodes). All of the current passes to our output, which will be equivalent to a logic 1 and read as HIGH. However, when one of the signals goes low, its diode will then conduct (since the cathode will be at GND potential and the anode will be at Vcc). This will leave only a 0.3 or 0.7 volt drop (depending on the type of diode) at the output, which is equivalent to a logic 0, and will be read as LOW.


There you have a basic description of the circuit I plan to use for the interrupter. This was more of a design entry rather than a build, so I will probably have to do another one. In all likelihood I will just send the board designs out to a vendor and have them made professionally, so there won't be much to see.

As always, thank you very much for reading, and feel free to leave any questions or comments below. I will be sure to get back to you as soon as I can.