ADC Using 555 Timer - Delta Modulator 2012-08-29

With the availability of the powerful micro controller in the modern era, people tend to forget the ordinary ICs. All the creativity has been replaced by the programming codes. This article illustrates the usefulness of the classic 555 timer as a Delta Modulator ADC.

Schematic



Parts List (main):

555 timer – NE555 x 2
Resistor – 100, 680, 740, 3.3k x 2, 10k, 47k, 51k
Capacitor – 47n, 100n x 2, 3.3u x 3
Diode – 1N5817
PNP transistor – 2N3906
Voltage source – 9Vdc

Parts List (simulation purpose):

Resistor – 10 x 3, 1k x 3
Capacitor – 75n, 80n, 85n
Voltage source – Since wave 2.4 peak (max), 200 to 2kHz

Theory of Operation

Astable multivibrator

The first 555 timer, U1 is configured as astable multivibrator. R1, R2, and C1 determine the oscillation frequency, which is 10 kHz with the formula below:

(R1 + R2) x C1 x ln2

D1 is used to bypass R2 when C1 is being charged up, to get 50% or less duty cycle. C2 is used to reduce the noise. R5 and C6 form a RC network to reset U1 first upon power up before performing anything else.

The output of the 555 timer, pin3 is used as the sampling clock source at the next stage.

Delta Modulation (ADC)

By using the internal comparators, a 555 timer can be configured as a Delta Modulator to perform Analog to Digital Conversion.
From the schematic above, V2, V3, V4, R8, R11, and R12 are the analog input signal (200 to 2kHz, 2.4Vpeak max) for this experiment. The analog signal is injected through C3 to CV (5) pin of U2. Since the CV (5) pin is the access to the internal voltage divider resistors network, it can be used as a level shifter for the input signal that swings up and down 0V.



With a coupling capacitor externally, the signal that goes into the 555 timer will be swinging above and below 6 V. If the original input signal is 2.4 Vpeak which is the maximum allowed, the shifted signal will be from 3.6 V to 8.4 V, which is in the range of 0 V to 9 V.
The inverting input of U21 has direct connection to the CV pin, which is the input signal + 6 V. Meanwhile, the non-inverting input of U22 is having half of the voltage level at the CV pin.

Q3 is turned on through R3 when the output of U1 goes low. C4 will then be charged through R4 towards the voltage level at CV pin of U2. When the output of U1 goes high, Q3 is turned off and C4 is holding the charged voltage level and feed into THRS (6) pin of U2. At time same time, R6 and R7 form a voltage divider to divide the voltage to almost half of that to THRS pin to the TRIG (2) pin.

With Q3 turned off, both present and previous values are obtained and ready to be compared for Delta Modulation.



When Vin is higher than Vin (t-1), the output of U2 is set high; while when Vin goes lower than Vin (t-1), the output is reset to low.

Rising -> 1
Falling -> 0

Note that R6 and R7 are not the same value but 47k and 51k. The reason for not having the same value is that the slope surrounding the peak of the input signal is not high for sinusoidal wave; the difference is not much for the previous and the present value. So one side is forced to be slightly higher to avoid having unknown state at the peak.

C5 and R9 are to reset the 555 timer at the power up.

Experiments

Bright green – original input signal
Blue – Delta Modulation output
Red – Present voltage level
Bondi blue – Previous voltage level

200 Hz 2 Vpeak


1000 Hz 2 Vpeak


2000 Hz 2 Vpeak


200 Hz 1.5 Vpeak + 1000 Hz 1 Vpeak + 2000 Hz 2 Vpeak


R13, R14, R15, C7, C8, and C9 are configured as low pass filter with the cutoff frequency of approximately 2 kHz, which is the maximum allowed frequency. The low pass filter at the output to demonstrate how can the Delta Modulated signal be demodulated (DAC). The pink waveform is the DAC output.





Note

Input signal has to be within the range of 200 Hz to 2 kHz. Delta Modulation requires sampling rate to be higher than Nyquist Sampling rate. Lower frequency have very little difference in the present and previous value which make it hard to compare.

Input signal should be anti aliasing filtered.

Maximum peak voltage of the input signal should not be more than 2.4 Vpeak.

The simulation is done in LTspice IV and has not been tested in actual world.