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Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
Hello everyone,
I'm doing parasitic capacitance simulation of a SiC half bridge power module. I made a hierarchical block which represents the MOSFET in each switching position. But when I tried to run the simulation, a warning occurred, saying the Tj_MOSFET port in the block was unused, I...
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