Hey,
I was trying to design a 2-bit up/down counter using gates, and came up with the following design:
When SEL = 0 & CLK = 1 : Output <- Output + 1
When SEL = 1 & CLK = 1 : Output <- Output - 1
When CLK = 0 : Output remains unchanged.
*The DELAY block comprises even number of INV gates.
What is your opinion?
Will it work?
I'd also love to hear any other suggestions you might have.
Thank you![Smile :) :)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
I was trying to design a 2-bit up/down counter using gates, and came up with the following design:
When SEL = 0 & CLK = 1 : Output <- Output + 1
When SEL = 1 & CLK = 1 : Output <- Output - 1
When CLK = 0 : Output remains unchanged.
*The DELAY block comprises even number of INV gates.
What is your opinion?
Will it work?
I'd also love to hear any other suggestions you might have.
Thank you
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