E EngIntoHW Member Sep 4, 2010 #1 Hey, I was trying to design a 2-bit up/down counter using gates, and came up with the following design: When SEL = 0 & CLK = 1 : Output <- Output + 1 When SEL = 1 & CLK = 1 : Output <- Output - 1 When CLK = 0 : Output remains unchanged. *The DELAY block comprises even number of INV gates. What is your opinion? Will it work? I'd also love to hear any other suggestions you might have. Thank you Attachments 2-bit up-down counter using gates.png 25.9 KB · Views: 1,837 Last edited: Sep 4, 2010
Hey, I was trying to design a 2-bit up/down counter using gates, and came up with the following design: When SEL = 0 & CLK = 1 : Output <- Output + 1 When SEL = 1 & CLK = 1 : Output <- Output - 1 When CLK = 0 : Output remains unchanged. *The DELAY block comprises even number of INV gates. What is your opinion? Will it work? I'd also love to hear any other suggestions you might have. Thank you
MikeMl Well-Known Member Most Helpful Member Sep 4, 2010 #2 Here is how I would do it. I used a modified Johnson counter. It is synchronous, and Grey-code, so can be decoded glitchlessly. It counts up as long as UP is true, and counts down as long as UP is false. It changes state on rising edges of Clk. Attachments 2BitUPs.png 332.4 KB · Views: 585 2BitUD.png 43.8 KB · Views: 767
Here is how I would do it. I used a modified Johnson counter. It is synchronous, and Grey-code, so can be decoded glitchlessly. It counts up as long as UP is true, and counts down as long as UP is false. It changes state on rising edges of Clk.