This is a simple gating problem so you don't need a special IC (I doubt that you'll find one anyway). Draw Karnaugh maps and devise the simplest realisation.
Don't know what a Karnaugh map is? Try searching for it in this forum or Google.
This decoder could be implemented in a single PAL IC, like PALC16V8 using VHDL language and her is the code for it
library ieee ;
use ieee.std_logic_1164.all;
entity decoder is
port (
a, b, c : in std_logic ;
y : out std_logic_vector (1 downto 0) ) ;
end decoder ;
architecture behavior of decoder is
signal abc : std_logic_vector (2 downto 0) ;
begin
abc <= a & b & c ;
with abc select y <=
"00" when "000",
"01" when "001",
"10" when "011",
"11" when "111",
end behavior ;