Well, say you have several memory chips on the same bus. Let's say there are eight data lines, D0 to D7 on each chip, for simplicity. Let us think about having two pins on each of these memory chips which controls the tri-state data pins. Now, if we want to write data to the memory chip, we use those two pins to set the tri-states to inputs, and put our data on the bus. If we want to read from the memory chip, we set the tri-states to outputs, and read the data from the bus. If, however, we do not want to read or write from or to this chip, we set the tri-states to high-Z, and it will appear, for all intensive purposes, that this chip is not on the bus. This way we can have multiple memory chips all sharing the same data bus. Hope this sheds some light on it.