:lol:
Is risky because the reset pulse is very short. When the decoder logic will sense 60 for ex, the reset output will go 1, as result the conter bistables and eventually other structures will start the reset process, but if one bistable is faster and other is slower then the faster bistable will be reset, the 60 combination will be change and the output of decoder logic will go in 0, in some defavorable cases before the slower bistable finish the reset process. For fix this potential problem a D flip-flop is inserted between ouptut of decoder logic and the reset input of counter, this flip-flop hold the reset level for half of clock period typical. Also a decoder with a high enough propagation delay can be used in place of flip-flop.