7490 counter digital clock buttons...........

what will be the pin configuration for 7400 ........ and how can we use and gate ic......can you plz clearify,,,.............

what will be the pin configuration for 7400

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Download a datasheet and see.

hey i hav downloaded the data sheet only the difference is of pin 14 in cmos its "vdd" and in ttl "Vcc" and rest of the connections are same........?????.........one more thing can you help me in understanding the logic behind using nand gate..........

Hi there,

Dont worry about it too much, i dont think a Nand type gate will work either.

The Nor gate wont work because the output of the normal clock circuit bit is sometimes high for relatively long periods of time which prevents clocking with the push button. The Nand gate will fail for the same reason only this time when the normal clock circuit bit is low, not high. So the same problem will persist just for different seconds counts.

A the very least the type of gate required is an "Exclusive Or" gate, and the push button must be held at a 'low' when not setting the time. This means the push button goes high for the first push, then back low again when released (if not then invert the push button signal).
The button operation will be a little unusual, because it will clock sometimes when you push it and sometimes when you release it but it will in fact work. You can also look for a better solution, but an exclusive or gate will not require any caps unless you have to also debounce the button. You can connect this new type of gate the same way you have the old 'or' gate connected now.

Another way to set time is to use the single input at the seconds input and use a higher frequency when you want to set the hours, then a somewhat lower frequency when you want to set the minutes. The advantage here is you dont need switch debouncing if you use a very short low pulse to clock during time setting.

Dont forget though that if you use an exclusive or gate as suggested you definitely have to have the push switch output a constant 'low' when not setting the time to prevent clock pulse inversion. If it happens to be high, then use a spare gate section to invert it.

Mr Al can u explain how xor gate will work............what will be its connections with the push buttons.......thanks

Hi again,

I mentioned in my post that you can connect it the same way you have the 'OR' gate connected now. You will probably need some switch debouncing too however if you dont already have that.

The exclusive OR gate works because of the way the input states generate the output states as seen in its truth table:

AB C
00 0
01 1
10 1
11 0

If we call input A the push button and it is low and input B the clock bit, the clock bit passes through the gate unchanged as shown by output C.
If the clock B stays low, a push will make A go from 0 to 1, which means the output C will go from 0 to 1, so when the push button is released the output will go from 1 to 0 and clock the counter. If the clock bit B stays high, a push will make A go again from 0 to 1 which means the output C will go from 1 to 0 which will clock the counter, then when we release the button A will go from 1 to 0 which will make the output C go from 0 to 1 which will not clock the counter.
Thus, we get one clock pulse as usual when the button is low, and we're guaranteed one clock pulse when the button is depressed and then released. If we push and release the button several times we'll get several clock pulses.

The Nor gate wont work because the output of the normal clock circuit bit is sometimes high for relatively long periods of time which prevents clocking with the push button. The Nand gate will fail for the same reason only this time when the normal clock circuit bit is low, not high.

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That would be true only if the QC output were used directly as the NAND input and is precisely why caps C3 and C4 were introduced in the circuit in post #17, to convert an otherwise prolonged signal to a brief pulse !

rest of the connections are same.

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Not so. For the CD4011, pins 1,2,5,6,8,9,12,13 are data inputs; pins 3,4,10,11 are outputs.
For the 7400, pins 1,2,4,5,9,10,12,13 are data inputs; pins 3,6,8,11 are outputs.

one more thing can you help me in understanding the logic behind using nand gate

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For the circuit shown:
When pin 1 goes Lo (Mins button pressed) OR pin 2 goes Lo briefly (Seconds count = 60, low pulse duration determined by R4,C4), pins 3,12,13 go Hi so pin 11 goes from Hi to Lo to clock the Mins count. A similar sequence happens for the Hours setting/clocking using the other two gates of the 4011.

MrAl's suggestion has the advantage that caps C3 and C4 would be unnecessary.

Hi alec,

Yes, if you add the two caps you get little one shots and that keeps the normal clocking pulse from holding one of the inputs in a state that freezes the pushbutton, but that also requires two additional resistors too. There's also a small concern about the input when the normal clocking pulse changes state...does it overdrive the input? We'd have to check that for both high-to-low and for low-to-high transitions.

The debouncing is a good idea, i guess he didnt have any of that yet? I was wondering about that too.

There's also a small concern about the input when the normal clocking pulse changes state...does it overdrive the input? We'd have to check that for both high-to-low and for low-to-high transitions.

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C3 or C4 can drive the gate input beyond the +ve rail voltage, but as it's only 10nF it doesn't have enough stored energy to harm the gate input protection diodes (at least, so far I've been lucky when using 10n in similar situations !). If the OP is really concerned then a limiting series resistor between the cap and the gate input, and external diodes from the input to the power rails could be provided. That's starting to look less elegant than your XOR proposal.

Hi alec,

Yes, a 10nf cap shouldnt bother the inputs too much, i just like to cover the bases.

We should see less than a 0.001 degree C increase in temperature for each push, meaning we'd have to push the button 1000 times to see 1 degree C rise in the die. I dont think that is too bad

Yeah with the XOR i was looking for a plug in replacement so nothing had to be rewired either, but it looks like he needs debouncing too which brings us to that topic. It appears that the Schmitt Trigger gates are better for signal conditioning and debouncing but im not sure if they make a XOR gate with Schmitt Trigger inputs. There's a chance that with the slow rising cap charge or discharge we might see multiply clocks getting through, which would mean setting the time could be a problem. A Schmitt Trigger hex package would clear this up, but that's another package then.

There's a chance that with the slow rising cap charge or discharge we might see multiply clocks getting through

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Slow rising cap charge is no problem as the 7490 is negative-edge triggered. Cap C1 or C2 is shorted by button actuation, so discharges very rapidly (say 10 Ohm x 100nF = 1uS) to give a good negative edge, with a re-charge time constant of 100nF * 100k = 10mS for debounce.
Cap C3 or C4 discharge also gives a sharp negative edge (as fast as the 7490 switches, say 100nS), with a re-charge time constant of 10nF * 10k = 100uS.

The time constants I used in post #31 were based on use of CMOS logic. If the OP wants to use TTL logic the debounce function will need re-thinking.

alec_t said:

Slow rising cap charge is no problem as the 7490 is negative-edge triggered. Cap C1 or C2 is shorted by button actuation, so discharges very rapidly (say 10 Ohm x 100nF = 1uS) to give a good negative edge, with a re-charge time constant of 100nF * 100k = 10mS for debounce.
Cap C3 or C4 discharge also gives a sharp negative edge (as fast as the 7490 switches, say 100nS), with a re-charge time constant of 10nF * 10k = 100uS.

Click to expand...

Hi again,

Yeah, and why would that change things? It doesnt matter what edge we deal with, if it's slow it could be a problem. Strictly speaking, it's not good design practice to allow a slow rising or falling clock and it doesnt matter what edge the clock triggers on. It has more to do with not allowing the slow changing signal to remain in the 'no mans land' band where the logic signal is undefined than it does with the actual edge...any edge trigger polarity would present the same design challenge. The analysis is not based on the particular clock edge, but is more like that of a biased logic input: we wouldnt want to bias our 5v logic inputs at 2.5v for the same reason. A slow changing clock signal is like an input bias where the bias doesnt last forever but it has some significant time duration which is more than the required rise or fall time. There's some spec for TTL as well as CMOS, and also for PIC clock inputs. Going beyond the spec means taking a chance on more than one clock taking place when only one clock pulse was intended. This is standard design practice. For example, if the spec is 20ns max rise time and we use a 250ns rise time, we can expect problems. This brings in the use of the Schmitt Trigger logic gate. It can handle things like this and output a clean signal. That's exactly what it is made for.
A similar design problem would arise if trying to drive the logic clock input with a standard op amp. The op amp's output signal can not change fast enough to satisfy the input clock rise (or fall) time, so the op amp output signal would have to be cleaned up with a Schmitt Trigger gate of the appropriate logic family.

Luckily this is only a pushbutton though, so it might not matter that much if a few extra clock pulses got through. The real world result might be that when the button is pressed to set the time to "15" minutes, it goes to say 12, 13, 14, then skips to 16 because at that point it got two clocks instead of one.

You're quite right. I stand corrected re the rising edge. That shows the value of a forum such as this: we can all learn.
So, Schmitt triggers it is. Swap the 4011 for a 4093 (one of my favourite chips, in view of its versatility)? Which XOR chip would you use MrAl?
What started off as a relatively straightforward design problem is becoming more complex if we're looking for the perfect solution.

Hi alec,

I dont see an XOR gate with Schmitt Trigger inputs so we'd either have to find one somewhere or else use a separate package for the edge cleaning operation.
Also possible is a pushbutton with two contacts (SPDT) if available to use with a SR Flip Flop...makes a really nice debouncer.

i am totally confused gentlemen. ...............can u explain in a bit easier manner and what will be the final solution of this problem...........

Well my final solution would be the circuit I suggested in post #17, modified by using a CD4093 instead of the CD4011 shown.
Over to you, Mr Al, for your final solution.

ic 4093 is a schmitt trigger nand and its ttl variant is 74132 ic ...........why is the diode logic not working with the butttons................

schematic

hey i hav made a schematic with diode logic apart from switch debouce portion plz see ....................can this logic be implemented with buttons ........ plz correct if required in this schematic...............

Pressing either button will probably place too great a load on the clock oscillator and prevent it working.
The osc output pin is being driven by both the internal osc circuit and by QC, so there is conflict.
If QC is at logic 1 the button can not change the Ck input to logic 0 without shorting QC via D1.