https://www.nxp.com/acrobat_download/datasheets/74HC_HCT595_4.pdf
See datasheet (link above) for details.
Simply, it transfers the 8 parallel output bits of the internal shift register to the output pins on the device when the enable pin is active. The transfer occurs on the transition from logic 0 to logic 1 on the latch input. This is generally useful to ensure that the output bits are presented only when you want them to be and remain stored until you latch it again.