I'm assuming that 0000 0001 is LSB......MSB. When you decode a counter, even a synchronous one like this, you will get glitches from your decoder (AND gate). This is clocking your reset FF. Try the following:
1. Move your start switch to Reset on the FF.
2. Reset the counter from ~Q.
3. Connect the output of your decoder gate to the D input, instead of to clk.
4. Clock the FF.
This will make your reset synchronous, avoiding the glitch. You may still occasionally have problems on startup, because the removal of the reset is not synchronous.
You need to move the LEDs to the collector circuits, in series with the resistors, and add a 10k resistor in series with each transistor base. The way you have it, you will only get about 2.7V logic 1 levels, with no predictable base current limiting. Your guaranteed worst-case logic levels (for LSTTL, anyway) will still only be about 2.7V (they will typically be higher than this), but at least you have predictable base current limiting.