877A to DAC (MCP4922)... SPI questions.

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ChemE

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As you can tell from the title I am working to connect a 877A to a DAC (an MCP4922). The 877A is the SPI master and the MCP4922 is the slave. Also as the title hints they are going to be connected through SPI. I have never delt with SPI before so I have a few basic questions.

First of let me mention that I through a search on this forum I found a fantastic presentation on SPI:
ww1.microchip.com/downloads/en/devicedoc/spi.pdf
The section showing the coding was great but there are a few questions that I could use some help with.

  • What is FOSC and TCY? How can I tell which one of the setting below to use for 877A to MCP4922?
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
  • Looking at the MCP4922 data sheet I noticed that it reads on the rising edge of the SCK. So I believe that the 877A would need to send its bits on the falling edge of SCK... am I right?

  • Is there something that I need to set to let the PIC know that it should send bits on the falling edge of the SCK or is that just how SPI works?

I used the SPI presentation to write code for the 877A, I feel pretty confident in it but...

  • The only other thing is if someone want they could take a look at the MCP4922 data sheet and see if there are any things that I may have overlooked that could cause me problems.

Thank you all, take care.
 

I'm actually an AVR guy, but I can take a stab at your questions.

  • What is FOSC and TCY? How can I tell which one of the setting below to use for 877A to MCP4922?
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2

I couldn't find any reference to FOSC in either the SPI doc or the MCP4922 datasheet, but it probably refers to your processor clock frequency and TCY is a time period - perhaps the time it takes to output one bit. The speed of SPI transmission is probably controlled by one of the PIC timers (TIMER2?), and that timer can be configured to run at various fractions of the processor clock frequency (like 1/4 or 1/16 or 1/64).


I think the way you expressed it is correct. The data bit has to be latched before the rising edge occurs. Also, from the timing diagram on page 9 of the SPI doc, the data line cannot change until the falling edge occurs so the only time the data line can change is after the falling edge.


I don't think you should worry about anything. SPI is a very standard protocol, and furthermore, all of your components (microcontroller, DAC and code) are supplied by the same company. so I think there's a very good chance it will just all work.
 
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