J Junker_eu New Member Jun 19, 2010 #1 Who knows the means of the sentence " always @ (1)" in verilog? Last edited: Jun 19, 2010
B BrownOut Banned Jun 19, 2010 #2 That only means the code block will continuously execute. This is a simulation construct that is ignored in synthesis.
That only means the code block will continuously execute. This is a simulation construct that is ignored in synthesis.