active or asserted input state in logic gates

Hi

Please have look on the attachment. Please help me with that para. The author uses the same terminology at other places. Thanks for the help.

Regards
PG

PG1995,

So what phrase, sentence, or word don't you understand? You should have specified what the problem is without me having to come back and ask you to elaborate. In the future, please be more specific.

Ratch

Hi there PG,

That means that when the input line is a certain state, something relevant to the application occurs.

For example, if we have no bubble on an input and that input is labeled "R0" that would mean "Reset to zero on high input level".
But if we had a bubble on that same input it would probably be labeled "R0" with a line over the top to indicate that we "Reset to zero with a low level input".

So the difference is whatever happens to 'activate' the input. The other state is considered 'inactive'.
So for R0 with no bubble a high is active and a low is inactive, and with R0 with a bubble (and usually a line over top of the R0 too) then we have an active low and inactive high.

It should be now clear that the level that causes the operation to take place (indicated by some other thing like a text label) is considered the active level, and the other the inactive level.

A couple other examples:

----- Reset (reset something on high level, dont do anything on low level)
-----o Reset (reset something on low level, dont do anything on high level)

----- Preset (Preset the count when this input is high, dont do anything when this is low)
-----o Preset (Preset the count when the input is low, dont do anything when this is high)

For a clock input we usually dont have a bubble when the clock makes the counter go to the next state when the input goes high,
but with a bubble it goes to next state when the input goes low. There is also usually a little arrowhead too with clocks.

Thanks a lot, MrAl. I think I understand it now. The way you put made it simple to understand. For example, have a look on the pinout diagram of 555 timer IC, it has a bar over the RESET which simply means that in order to reset the IC connect this pin to the the LOW state (I think by default pin #4 is connected to the HIGH).

**broken link removed**

@Ratch: Actually I was having problem with the highlighted portion of the text. I had highlighted some of the terms such as "active or asserted" and "active-LOW". Anyway, thanks for giving it a look. It's just that I wasn't clear enough.

Regards
PG

Hi PG1995,

actually there is no difference in function if you use an inverting designator for input or output. Both mean the input signal is reversed at the output or change functions within a chip.

Input H - output L, Input L - output H.

Pin4 of the NE555 will put the entire chip into standby if it is connected to ground or via a pulldown resistor. As soon as pin4 "sees" a logical "1" = "H" it will bring the chip to normal operation conditions.

Also take a look at the CD4017 (Johnson counter) Pin13(Clock inhibit) must be tied to VDD to inhibit counting. The counter advances one count with each positive going pulse edge if pin13 is tied to ground.

Boncuk

Boncuk

Ratchit said:

PG1995,

So what phrase, sentence, or word don't you understand? You should have specified what the problem is without me having to come back and ask you to elaborate. In the future, please be more specific.

Ratch

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