Altera and SOPC

[BrownOut]

Hello again, I'm using System On A Programmaboe Chip to build my system on an Alteria FPGA. After generating the system, I understand from Altera that I next need to hand generate a block level design that incorporates the system or else write a top level HDL file. Someone please tell me that is a joke! I can hardly believe I can generate an entire system with the tool, but not the top level entity.

I joined the EDA forum for this issue, but can't activate my account ( not this site ). So much for that baloney.

 

[BrownOut]

After two days of searching, I've found the answer:

1. In the Quartus II software, on the File menu click New.
2. Select Block Diagram/Schematic File and click OK. A blank .bdf, Block1.bdf,
opens.
3. On the File menu click Save As. In the Save As dialog window, click Save.
1 The Quartus II software automatically sets the .bdf file name to your project
name.
4. Double-click in the blank .bdf, point to Insert and click Symbol to open the Symbol
dialog box.
5. Expand Project, under Libraries select sopc_top, click OK.
6. Position the SOPC Builder system component outline in the <project>.bdf and
left-click.
7. Right-click on the SOPC Builder system component and click Generate Pins for
Symbol Ports, to automatically add pins and nets to the schematic symbol.
8. Click File-Save
9. On the Project Menu, click Set as Top-Level Entity.