Hello again, I'm using System On A Programmaboe Chip to build my system on an Alteria FPGA. After generating the system, I understand from Altera that I next need to hand generate a block level design that incorporates the system or else write a top level HDL file. Someone please tell me that is a joke! I can hardly believe I can generate an entire system with the tool, but not the top level entity.
I joined the EDA forum for this issue, but can't activate my account ( not this site ). So much for that baloney.
I joined the EDA forum for this issue, but can't activate my account ( not this site ). So much for that baloney.