On positive half cycles, the active circuitry consists of a saturating common-emitter stage consisting of R3, Q3, and R5. The other transistors are off. D1 keeps the Vbe of Q1 from breaking down in the case where Vcc is higher than the breakdown voltage (generally around 6V).
On negative half cycles, Q3 is off, and Q2 is a saturating common base stage. It has no current gain, and its collector voltage will be about -0.6V wwhen it is saturated. Q1 is an emitter follower, providing the current gain necessary to drive R5 and also the level shifting reqiured to keep the output slightly above 0V while Q2 is saturated.
Therefore, during both positive and negative half cycles of the input, the output is near 0V. When -0.6V<Vin<+0.6V, All transistors are off, and the output rises to Vcc, resulting in a short positive pulse during each zero crossing.
EDIT: I am not the **broken link removed**, although I had to do a little Googling to find it. I had reconstructed it from memory, and wound up with a slightly different circuit. The original is simpler, in that it doesn't require the diode. It also has more symmetrical rise and fall times, at least in simulation.