If you remove the emitter bypass capacitor C1, then the voltage gain of the stage would be approximately R3/R4.
That would seem to be good advice. Since the gain is low (5), it can be achieved without the emitter bypass capacitor. This would also reduce distortion. The arrangement shown is typically used for larger gain.
We can also note that the effective collector resistor Rc is R3 in parallel with the load resistance RL, once the output is hooked up to something.
Av=-Rc/R4 where Rc=R3*RL/(R3+RL)
This approximate formula requires that R4 be much greater than hib=Vt/Icq (Vt=KT/q which is about 25 mV at room temperature)
Of course, the circuit must be properly biased to allow full signal swing and stability to temperature changes, as well as insensitivity to beta changes. Just looking quickly, it appears that the 9VDC power supply will not allow full signal swing with 2V p-p input voltage and a gain of 5.
It's really difficult to explain all aspects to transistor circuit design in a forum. There are many textbooks on the subject. For example, I used Electronics Design by Savant, Roden and Carpenter back in school. Looking back at it now, it seems to be a good book to learn from. I'm sure other people can recommend good books.