Anyone using ISE Webpack?

I hit a snag with ISE Webpack from Xininx. There appears to be a bug that is evidently fixed in the purchase version of ISE, but I am getting it in webpack. Specifically, I get this when I try to synthesize a top-level design:

"ERROR:Xst:2033 - Port I of Input buffer <instance_name> is connected to GND"

Example

IOBUFDS lvds_ibufg_crystal
(
.IO(inp),
.IOB(inn),
.I(1'b0),
.O(outp),
.T(rst)
);

But Xilinx claims:

Solution
This issue is fixed in ISE 8.2i.

Click to expand...

Since I'm using ver 11.1, I should not be seeing this error message. Could it be that I'm using the free version of software, or maybe because I'm targeting Spartan3 technology?

I guess I could try it and specify Spartan6???? I'll give that a try is nobody has a better idea.

Nobody seems interested, but here is an update anyway:

I've researched the problem, and Xilinx suggests that an IOBUFDS be "blackboxed" for synthesis. What that means is, the synthesis engine does not actually syntheisze the library for the IO, but instead inserts a "place holder" sort of like the way a "C" compiler holds a place for functions that are defined for linking. So anyway, I created a top level module that defines the black box. However, it occured to me that the software should not be inferring this IO type, as all my signals are signle ended inputs or outputs ( no input/output ) In the mean time, I synthesized my design with IO Buffer insertion turned off, and it ran successfully. So I decided to trun that option back on and see if I can figure which signal the software is inserting the wrong buffer for. When I re-ran synthesis, it compleated successfully, and the correct buffers were inferred for all I/O's.

Man, that's BUGGY software!

Don't confuse lack of response as lack of interest, rather lack of having an answer I have no experience with the latest Xilinx software as last time I used Xilinx was with Synopsys. I am sure free software will have its share of bugs but as I can recall, Xilinx field reps were Johnny on the spot to offer assistance. Their tech support hotline use to be a good place to get answers--do they still have this? Well glad you found a workaround.

Ok, here is a related question, that some of our PIC master might be able to answer. My development system uses an LCD display with a built-in sitronix **broken link removed** graphics controller. Looking over the initialization procedure, I've found this following, for the 4-bit interface:

POWER ON
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 1 X X X X (Brownout: This sets up an 8-bit interface)
Wait time >40mS
After Vcc >4.5V
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 X X X X (Brownout: This sets up a 4-bit interface)
0 0 N F X X X X X X
Wait time >37uS
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 X X X X (Brownout: This sets up a 4-bit interface)
0 0 N F X X X X X X

(rest of initialization...)

So, it requires a command for 8-bit interface (although I have only 4 bits to work with) followed by two commands for 4-bit interface. Why do I need to do it like this? Why not just a single 4-bit interface command?

Here is 8051 code for the initialization:

CALL DELAY40mS
MOV A,#38H ;FUNCTION SET
CALL WRINS_ONCE ;8 bit,N=1,5*7dot
CALL DELAY37uS
MOV A,#28H ;FUNCTION SET
CALL WRINS_NOCHK ;4 bit,N=1,5*7dot
CALL DELAY37uS
MOV A,#28H ;FUNCTION SET
CALL WRINS_NOCHK ;4 bit,N=1,5*7dot
CALL DELAY37uS

PS: My user guide has a different, yet equally illogical method for setting up the controller:

1. Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
2. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
3. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
4. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
5. Wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
6. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
7. Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
8. Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles.
9. Wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.

Click to expand...

So, Xilinx says to issue 3 8-bit setup commands followed by a single 4-bit setup command!

I be confused and stuff

Ok one more question; anyone use Model Sim free simulator? Any thoughts? Are the better/competitive products?

Here is an update: I finally got the design for the tutorial to configure and work. It was actually created for a different development system, so there were some modifications to make. Also, I was unwittingly using the wrong pinouts for my system. The correct one was damn hard to find; I had to find the "advanced" document search application on Xilinx website to finally track it down. Until then, I only had the schematic to work from.

So... the design is for a simple "stopwatch" with lap recording. The LCD is used for output and interface. The glaring problem with the design is the display logic was done with "brute force" and not portable to other designs. So... the next job is to create a LCD module along with a data memory and simple protocal that can be used in later projects. This is important because the LCD will be a great debugging aid as I go forward.

I suppose I should just turn this into a blog.

**broken link removed**