Beginners question about Active High and Active Low

Hello,

Just wanna make sure I understand active high and active low properly.
If I were to use an active high and use a voltages of 5v and 0v then
5 would represent a 1 and 0V would represent a 0.

and
If I were to use an active low, then 0V would represent a 1 and 5V would represent a 0.
Do I understand it correctly?

Thanks,

Ben

I read on a website that you can change from active high to active low at will, is that right? how is that possible?

Your first question. Not exactly. Every logic family has it's own definitions of High and Low and sometimes a grey state where neither is defined. CMOS is effectively rall to rail except for TTL compatable CMOS.

I want to warn you that:
1. Active low
2. Active high
3. Open collector
4. Tri-state
5 open drain

are all output styles.

I won't go as far as active high to active low at will, but it is possible, for example, when defining ports on a microprossor to have them
1. Start out as Tri-state
2. Configure them as an input or an output.

Sometimes it makes things difficult, so the ULN 2003, U:N200x etc relay drive can come into play. These devices are optimized per logic family. It can cause issues with TTL because inputs float high. In that device...

1. Unplugged - Open collect off
2. A high input - Open collector ON
3. A low output - open collector OFF

alphaai said:

I read on a website that you can change from active high to active low at will, is that right? how is that possible?

Click to expand...

You can define a voltage high or voltage low as logic 1 as you desire. It's simply a matter of definition. You just need to be aware of your definition so as not to confuse things.

An example of this is changing the definition to allow you to use the same logic gate for different functions. For example a standard AND or NAND gate for high = logic 1 can perform as a OR or NOR gate for low = logic 1. Similarly a standard OR or NOR gate for high = logic 1 becomes an AND or NAND gate for low = logic 1. This can sometimes allow you to minimize the number of different type of gates you need, or it can avoid having to invert signals for the desired logic function.