I am building a binary clock and i have a problem when it counts it acts strange i have included the schematic but the situation is when it resets at 60 it starts the count over at zero so it counts like this ...55, 56, 57, 58, 59, 00, 00, 01. the counter resets at 60 but then the count starts at zero i need it to start at one.. any ideas?
I am building a binary clock and i have a problem when it counts it acts strange i have included the schematic but the situation is when it resets at 60 it starts the count over at zero so it counts like this ...55, 56, 57, 58, 59, 00, 00, 01. the counter resets at 60 but then the count starts at zero i need it to start at one.. any ideas?
It works, it just counts zero twice it resets at 60 so it does not show 60 (because it resets so quick) and it displays this 55, 56, 57, 58, 59, 0, 0, 1. i need to know if there is a way to make the flip flops start at 1 instead of 0. so it will count like this 55, 56, 57, 58, 59, 0, 1.
well you do want to start at 0, but it shouldn't be counting twice, the problem is obviously in your reset circuit, may I suggest putting the AND gate on to the NOT Q 's
then you can remove your NAND chip.
It's pretty easy in this case to imagine one or more of the counters not getting reset by the very short "60" pulse. You might consider a short one shot to make sure (>40 ns). Otherwise it looks like one should come on with the 1st rising edge after the 60 glitch.
It works, it just counts zero twice it resets at 60 so it does not show 60 (because it resets so quick) and it displays this 55, 56, 57, 58, 59, 0, 0, 1. i need to know if there is a way to make the flip flops start at 1 instead of 0. so it will count like this 55, 56, 57, 58, 59, 0, 1.
hi,
Checking your circuit, you are not showing resistors in series with the LED's,use 220R's.
As you say on the 60th clock pulse, the reset AND gate resets the count/display to '0', [all LED's OFF] which it should do and should hold '0' until the next clock pulse.
At the next pulse the first counter will switch from '0' to '1' which is what you want.?
Are you clocking at 1Hz.?
no it is not clocked at 1Hz yet I have not built that part of the circuit, do you think that is the problem? And from the way I am looking at it if I run the not q's to and and gate to the clears then it will keep it contantly clear because the clear input will be recieving a low
no it is not clocked at 1Hz yet I have not built that part of the circuit, do you think that is the problem? And from the way I am looking at it if I run the not q's to and and gate to the clears then it will keep it contantly clear because the clear input will be recieving a low
Clear to output time is 13ns typical. This says your reset pulse will be around 13ns. Clear minimum pulse width 25 ns. These 2 don't go together. The one count is not getting reset at 60 so it takes another clock to get it to 1. Anything else happen between 60 and 1???