U4 - the connection between Q9 and the reset input does not do anything. When Q9 goes high, forces a reset, and then is yanked low by the reset, both Q7 and Q8 have just transitioned to low anyway.
The clock into U7 is capacitor coupled. Why? There is no DC reference for the input.
The output from the analog switch has a unknown value capacitor to GND. Why?
The clock into U7 (and hence the data rate into the D/A, does not change when the analog switch is switched. It is tied to the 15.5 kHz input at all times. This is the reason the circuit is not doing what you want. In 60 Hz mode you are terminating the data cycle half way through the full pattern. To have the D/A make the full pattern in half the time, the data needs to arrive twice as fast. This means doubling the clock freq into U7, not simply resetting it sooner.
ak