hi,
The top of the 10K has to go to the +V, so that on power up the FF is cleared.
You will have to use an OR gate to combine the output of the Res/Cap and the logic Clear.
You could use a NAND for U6A/5A, but as a designer you should consider the total ic count.!
EDIT:
Look at this image, its not been fully checked, but should suggest a solution.