Can you provide a better picture of 12 bit DAC to 8 bit data bus or explain the address decoding?

The byte1 /byte2 line is in effect "A0", selecting which of the input latches is written to when /WR1 is activated.

As those have to be loaded during separate instruction cycles, if they were directly linked to the DAC, it would have part of the new value and part of the old value between those two cycles.

The second latch can load all 12 bits at the same time, when the /XFER and /WR2 signals are activated.

The full address decode to set the physical addresses the DAC setup operates at is not shown.


Note that this setup could be simplified, with just one latch and the other data lines straight to the DAC register; load the latch then write the DAC register, which would take the latched data for one half and the new data for the other.

That's how 16 bit peripheral transfers are done in some MCUs; eg. write a holding register for the high half of a word, then write the low half to another register, which also transfer the stored high byte.

It looks like you write into both latches when pin-14 =1, and only write to the 4- bit latch when pin14 = 0.
Write the 8 bit first, then the 4 bit latch!

ronsimpson said:

It looks like you write into both latches when pin-14 =1, and only write to the 4- bit latch when pin14 = 0.
Write the 8 bit first, then the 4 bit latch!

Click to expand...

The detail logic is strange.. The latch enable are shows active low, but the text says they are active high.

The 4 and 8 bit latches don't have an OE input so there outputs are either following the input or the latched value. This will cause contention on the bottom 4 bits. They don't need to latches at all and would be better using something like a 74244 octal buffer.

Mike.

Some of these datasheets go from language to language... But if pins 1 and 2 are low the output doesn't match the internal latch ergo the text must be right.