Cannot clear flag 'IE3' on 8051 microcontroller

[dyson]

I am just learning to program in assembly using the 8051 microcontroller, and I am working on a simple Jeopardy-style project in which I have two clickers and a reset button, and one of two LED lights turns on depending upon which clicker is clicked first.


I am writing the program for this using interrupts, so the reset button is the input for INT0, clicker A is the input for INT1, and clicker B is the input for INT3. (I went with INT3 rather than INT2 so that they would all be negative-edge triggered). I'm simulating my program on RIDE7, but I found that whenever I simulate an interrupt on INT3, I get stuck in a state in which the INT3 interrupt perpetually occurs. I figured out that this is because the flags associated with INT0 and INT1 are automatically reset after those interrupts occur, but the flag associated with INT3 is NOT reset.


According to the High Speed Microcontroller User Guide (attached), this flag is named IE3, and its description reads: "This bit will be set when a falling edge is detected on INT3. This bit must be cleared manually by software." (see p. 28) The problem is, I cannot for the life of me figure out how to clear it manually by software. In the Interrupt Summary Table 9-1 of the same guide (p. 107), it says that IE3 is located at bit 5 of the EXIF register.


So in my program I issued the instruction CLR EXIF.5 . Unfortunately, this generates the following error: INVALID BYTE BASE IN BIT ADDRESS EXPRESSION. I have also tried using the address of the EXIF register, so that the instruction is CLR 91h.5 ...and this still gives exactly the same error. I have also tried MOV EXIF.5, #0 . Nothing works. Any help would be much appreciated. Thanks in advance.

 

[Ian Rogers]

What chip are you using... When I use certain chips ( with extra registers... Most 51's only have two INT pins ) There is usually a work around...

Once I know the chip I'll take a look see..

 

[dyson]

I believe it is the Dallas DS80C320...does that make sense?

 

[Ian Rogers]

Yep..... Bit access is extremely limited on a 51... Only several registers are bit addressable... Unfortunately 0x91 isn't one of them. This is an extended SFR so the rules don't apply..

The way of dealing with these.... If you are using EX5, EX4,EX3,EX2 individually then just write clr EXIF. They are assuming that the conflicts between them is minimal...

 

[dyson]

Thanks for the response. Unfortunately, however, the instruction CLR EXIF generates the error: BIT-ADDRESS EXPECTED. (I am using the Raisonance RIDE7 simulator to assemble the code.) It seems I'm damned-if-I-do, damned-if-I-don't. Any ideas?

 

[Ian Rogers]

CLR EXIF generates the error:

Sorry... Of course it will.. My bad

Mov EXIF,#0h may do the trick....

 

[Jon Wilder]

Probably because the bit address is not predefined in a header file within the tool chain you're using.

0xE9 being the address of the EX2 bit in the EIE register, try -

        clr       0xE9

Or you can do an AND operation -

        anl        0xE8,#0xFD       ; clear EX3 bit

 

[dyson]

Yes, Mov EXIF,#0H worked! (future forum readers: note that that is a zero, not the letter 'o') Thank you very much for the help, Ian Rogers.

Jon Wilder, thanks for the idea, but (if I understand correctly) clearing EX3 will permanently disable interrupts via INT3, so that after an INT3 interrupt happens once, EX3 will be cleared, and no INT3 interrupt will be able to happen again. I wanted an INT3 to be able to happen again--just not be perpetually happening all the time.

 

[dyson]

Also, the instruction ANL EXIF, #DFH will reset just the bit we want to reset, and leave the rest alone.

 

[Ian Rogers]

Also, the instruction ANL EXIF, #DFH will reset just the bit we want to reset, and leave the rest alone.

Shouldn't need to really... Unless the interrupt is lower than the others.... If EX2 occurs when you are servicing EX3... But as you are only using 1 interrupt in this register, the command to mov will suffice..

 

[Ian Rogers]

Jon... The EIE register is already bit accessible... 0xE8.... any SFR that ends in 0 or 8 is bit accessible.. ie E8 D8, A0 etc...