Charge Pump Design

[kinarfi]

Are there any standard rules/suggestions to use when putting a Charge Pump together? such as start with small caps and then go larger, use the same size through out, start big and go smaller. I plan to just use a totem to power it and trigger fets with a 36K Hz square wave. I need to double my twelve volts to drive the upper fets of an H bridge.
Thanks,
Kinarfi

 

[MikeMl]

Are you talking about the two-capacitor, two diode charge pump that looks like this:

 

[kinarfi]

More like the first and exactly like the .asc file. I was going to use an LT1270 and an inductor & cap, but every time the LT1270 recharged the cap, it created spikes on the oscillator wave form which I would like to have as clean as possible. This method uses the one oscillator for everything.
Thanks,
kinarfi
PS, are you missing the inversion up here?

 

[kinarfi]

Here's the drawing of the .asc , I may have some components in my library that I have modified or that others don't have.
As I try different combinations in Spice, it appears that starting big and going small gives the quickest charge time.

 

[MikeMl]

Not missing the Inversion at all. It was 20degF early this morning, but it got to about 60degF by early afternoon. Wall to Wall blue sky and visibility about 150mi.

The thing in your posts looks like a voltage tripler. What I posted is a doubler.

Looking at your H-bridge, what is the Gate to Source breakdown voltage for the FETs you are using. It looks like Vgs could be as high as 40V in your circuit?

 

[misterT]

I need to double my twelve volts to drive the upper fets of an H bridge.

So, your real question is "How to drive high side N-channel FET". This is called bootsrapping. Take a look this pdf, specially pages 22-28.
**broken link removed**

Of course, if you need to keep the FET on for a long time (i.e. this is not a switching application), then using a separate charge pump to provide the gate drive voltage is a good idea. In that case read pages 18-22.

 

[kinarfi]

Not missing the Inversion at all. It was 20degF early this morning, but it got to about 60degF by early afternoon. Wall to Wall blue sky and visibility about 150mi.

The thing in your posts looks like a voltage tripler. What I posted is a doubler.

Looking at your H-bridge, what is the Gate to Source breakdown voltage for the FETs you are using. It looks like Vgs could be as high as 40V in your circuit?

VGS is + or - 20 and so far Spice has shown that it doesn't get any higher than 12v, FETs IFR3205 by ST

 

[kinarfi]

The thing in your posts looks like a voltage tripler. What I posted is a doubler.
Looking at your H-bridge, what is the Gate to Source breakdown voltage for the FETs you are using. It looks like Vgs could be as high as 40V in your circuit?

You said that it looked like I had a voltage tripler, it seems each stage only adds 50% of the supply voltage.
Are there any guide lines for choosing the size of the capacitors.

 

[ronv]

I think the rule of thumb is that the caps should be 10X bigger than the gate capacitance. The frequency higher than the switching frequency of the pwm.
A 555 works good for this - can drive quite a bit of current and is it's own oscillator.

 

[kinarfi]

I think the rule of thumb is that the caps should be 10X bigger than the gate capacitance. The frequency higher than the switching frequency of the pwm.
A 555 works good for this - can drive quite a bit of current and is it's own oscillator.

Do you see any problem of using the same oscillator for every thing as I have done in post 4?

 

[audioguru]

Your Mosfets are not switches, instead they are source-followers (they do not invert) with +10V peak input and maybe only +5V or less peak output.

 

[kinarfi]

YES, my design was not working when tested, so I dug through the old post and found a design posted by alec_t (Thank You)
https://www.electro-tech-online.com...aveform-woes-load-switch.122607/#post-1012385
post #13

.....which is precisely the circuit shown in post #2.

Although the post #2 circuit provides fast FET switching it does gobble current during the pulse edge transients, when both the NPN and PNP are conducting at the same time briefly. By swapping the NPN and PNP positions in the totem pole that transient current is eliminated, at the expense of slower FET switching. Attached are the two arrangements for comparison, plus the .asc file (as requested by Aaron in post #9).

Headed for the garage to see if it works in reality as well as it does in Spice.