Clock Recovery PLL

[DMullinsL3H]

I am debugging a design to recover the clock from an incoming data stream using a "Hogge" phase detector. This type of detector works with NRZ data as well as Manchester, which we are using and guarantees one level transition for every bit. The phase detector feeds two signals into a filter, one has variable pulse width proportional to the phase between the local VCXO clock and the incoming data, the other has either one or two lows and highs for every incoming bit. This is filtered yielding a ramp at the max beat frequency of the local clock and expected data clock when the signals are at the worst case delta frequency. The filter Fc = the max beat frequency and it is amplified to a full rail-to-rail signal. As the local clock gets close to the data clock frequency, the ramp levels out and becomes an indicator of phase. After the filter and amp is a LPF integrator that provides out of band attenuation and high LF gain (sub 1 Hz).

We have a ~50MHz local VCXO, divide by 3 feedback loop (50% duty cycle), ~16.667MHZ PD input clock, ~8.333MHz incoming data bits (0 data bit = 1 clock cycle high and 1 clock cycle low; 1 data bit =1 clock cycle low and 1 clock cycle high). This design is to replace a working design to replace obsolete components.

This is locking and working very well, except for one thing. It should be locking such that the rising edge of the local clock is synced with the midpoint of the incoming data bits (to guarantee setup time for latching each bit into the registers). Instead, it is syncing with the rising edge of the data. The pulse width signal, therefore is dithering back and froth from minimum width (clock is just after the data edge) to max width (clock is just before the data edge) and the filter is averaging this into a 1/2 VCC signal, just as if it was locked at 50% duty cycle pulse width.

What gives?

Sorry, I can't upload design specifics but here is a representative circuit, attached.

 

[DMullinsL3H]

I am using fast 3.3V logic, typical Tpd 2-3 ns.

 

[Tony Stewart]

8.333 Mbps BiPhase (?) or 16.666 MBps ?
16.666 MHz VCXO

Whenever I did this, the Clk & data rate was the same and edge-sensitive detectors always sync'd to data midbit transition while XOR mixers sync'd in the middle. Pls confirm

 

[DMullinsL3H]

8.33 Mbps data and 16.66 MHz clock into the phase detector. VCXO is 50 MHz and that is divided by 3 to get the clock input to the PD.

 

[aliarifat794]

Simulate the entire phase-locked loop, including the Hogge phase detector, loop filter, VCXO, and feedback divider. Use a tool like SPICE or MATLAB to model the system and analyze its behavior under different conditions.

 

[Tony Stewart]

I used to do this in the 70's just using a 3/4 T non-retriggerable one shot to sync off the clock edge and sample data polarity on the trailing edge for logic level Biphase Manchester coding.

But a PLL can be done with more stability so as to filter out input clock edge jitter using appropriate filters in the PLL.

There are many demodulator mixers from asynchronous , XOR , and analog synchronous multipliers. Thus depends on SNR vs desired BER probability, BW and eye pattern, window margin specs. if you have any specs.

 

[Teresad340]

Hi. I think your having issue with synchronizing your local clock to the incoming data. There might be a phase shift between them. You should try tuning your PLL loop to reduce the phase error. You can also check if there are any distrubances or noise on the data line that could affect the phase detector operation. If the problem persists, try modifying the circuit to sync the rising e dge of the local clock to the midle of the data bits. You can do this by adjusting the delay in the feedback loop or using an aditional sync circut. Let me know if any of those help. I'll be glad to assist further if you have more questions.

Regards
Teresa