DMullinsL3H
New Member
I am debugging a design to recover the clock from an incoming data stream using a "Hogge" phase detector. This type of detector works with NRZ data as well as Manchester, which we are using and guarantees one level transition for every bit. The phase detector feeds two signals into a filter, one has variable pulse width proportional to the phase between the local VCXO clock and the incoming data, the other has either one or two lows and highs for every incoming bit. This is filtered yielding a ramp at the max beat frequency of the local clock and expected data clock when the signals are at the worst case delta frequency. The filter Fc = the max beat frequency and it is amplified to a full rail-to-rail signal. As the local clock gets close to the data clock frequency, the ramp levels out and becomes an indicator of phase. After the filter and amp is a LPF integrator that provides out of band attenuation and high LF gain (sub 1 Hz).
We have a ~50MHz local VCXO, divide by 3 feedback loop (50% duty cycle), ~16.667MHZ PD input clock, ~8.333MHz incoming data bits (0 data bit = 1 clock cycle high and 1 clock cycle low; 1 data bit =1 clock cycle low and 1 clock cycle high). This design is to replace a working design to replace obsolete components.
This is locking and working very well, except for one thing. It should be locking such that the rising edge of the local clock is synced with the midpoint of the incoming data bits (to guarantee setup time for latching each bit into the registers). Instead, it is syncing with the rising edge of the data. The pulse width signal, therefore is dithering back and froth from minimum width (clock is just after the data edge) to max width (clock is just before the data edge) and the filter is averaging this into a 1/2 VCC signal, just as if it was locked at 50% duty cycle pulse width.
What gives?
Sorry, I can't upload design specifics but here is a representative circuit, attached.
We have a ~50MHz local VCXO, divide by 3 feedback loop (50% duty cycle), ~16.667MHZ PD input clock, ~8.333MHz incoming data bits (0 data bit = 1 clock cycle high and 1 clock cycle low; 1 data bit =1 clock cycle low and 1 clock cycle high). This design is to replace a working design to replace obsolete components.
This is locking and working very well, except for one thing. It should be locking such that the rising edge of the local clock is synced with the midpoint of the incoming data bits (to guarantee setup time for latching each bit into the registers). Instead, it is syncing with the rising edge of the data. The pulse width signal, therefore is dithering back and froth from minimum width (clock is just after the data edge) to max width (clock is just before the data edge) and the filter is averaging this into a 1/2 VCC signal, just as if it was locked at 50% duty cycle pulse width.
What gives?
Sorry, I can't upload design specifics but here is a representative circuit, attached.