cmos power dissipation

[rahe_wafa20]

i want to know which softwares we can use to estimate the CMOS inverter dynamic power at gate level. How can I find out the power by simulation.

 

[mneary]

If you are designing an FPGA, the vendor's FAE will have your best answer.

 

[rahe_wafa20]

actually i am studying 6T SRAM cell . which consists of two inverter.can u tell me any freeware

 

[Mikebits]

I always did it by hand. Figure in worst case.

 

[rahe_wafa20]

I always did it by hand. Figure in worst case.

yeah i am also trying to do so. can u tell me is that right approach.
i am using MOS level 3 three equations. we can find the load capacitance by adding all parasitic capacitances
and then adding all.
dynamic power = Vdd*Vdd*CL*f


pls see attached file.

 

[crutschow]

That's the correct way to calculate the power.