cmos power dissipation

R

rahe_wafa20

New Member

• May 15, 2010

• #1

i want to know which softwares we can use to estimate the CMOS inverter dynamic power at gate level. How can I find out the power by simulation.

 

M

mneary

New Member

• May 15, 2010

• #2

If you are designing an FPGA, the vendor's FAE will have your best answer.

 

R

rahe_wafa20

New Member

• May 15, 2010

• #3

actually i am studying 6T SRAM cell . which consists of two inverter.can u tell me any freeware

 

Mikebits

Well-Known Member

• May 15, 2010

• #4

I always did it by hand. Figure in worst case.

 

Last edited: May 15, 2010

R

rahe_wafa20

New Member

• May 15, 2010

• #5

Mikebits said:

I always did it by hand. Figure in worst case.

Click to expand...

yeah i am also trying to do so. can u tell me is that right approach.
i am using MOS level 3 three equations. we can find the load capacitance by adding all parasitic capacitances
and then adding all.
dynamic power = Vdd*Vdd*CL*f


pls see attached file.

 

Attachments

• These are the parasitic capacitances.doc

  85.5 KB · Views: 184

crutschow

Well-Known Member

Most Helpful Member

• May 15, 2010

• #6

That's the correct way to calculate the power.