collector output

1.can somebody tell y common emitter connection is more popular than d other two... and y is d output taken at collector..

2.pls xplain y bjt is called a current controlled device?

3.can somebody help me with design of freq multiplier using 566. phase locked loop... give some idea

I would appreciate if you could make an effort to type your words out fully instead of using abbreviations. For example, it would be better if you type "why" instead of "y" and "please" instead of "pls". It is more courteous to your reader if you do so as otherwise we must "interpret" your meaning.

However, if you are posting from your cell phone, then I will understand your use of abbreviations.

1. The transistor has three terminals. The emitter is common to the input circuit and the output circuit. The base is where the input is, so the only terminal left is the collector where the output circuit is. It is more popular at low frequencies because it provides current gain. That is a small base current controls a much larger collector current. 40 dB of current gain is quite common from garden variety transistors.

2. It is called a current controlled device because the output current, Ic, is controlled by the input current Ib. The constant of proportionality is called beta(greek letter), or hfe, or hFE. What is the difference?
Beta is the DC current gain at some operating point.
hfe is the small signal gain when the transistor is biased in it's linear region.
hFE is the large signal gain when the transistor's input takes it from saturation to cutoff and back.

3. A VFO creates a high frequency signal. A counter is used to divide the high frequency down to a lower frequency. That lower frequency is compared to a reference frequency, and the VFO frequency is adjusted up or down as a result of the comparison. That's it in a nutshell. The VFO frequency is a multiple of the reference frequency.

The divide by 5 output is connected to the phase comparator, which is incorrect. The divide by 10 output is pin 12.

Russlk said:

The divide by 5 output is connected to the phase comparator, which is incorrect. The divide by 10 output is pin 12.

Click to expand...

This is interesting so I looked up the LM565C from my 1980 NS Linear Application databook. Guess what? The PLL phase comparator pin 5 did get its signal from counter output pin 12(divide by ten).

So there is a delibrate change on the circuit configuration. But why?

The main difference of the present circuit wrt the 1980's circuit is that of the power supply arrangement. A single +12V supply was used back then for the PLL while dual supplies(+/-6V) for the present circuit. The decade counter supply remains unipolar(+6V or +5V) in both circuits.

Therefore the new arrangement could have something to do with the +/- swinging nature of the 10KHz frequency input(wrt gnd) but the unipolar output of the counter.

The phase detector requires a square wave signal to work properly, which is only available from the divide by 2 output, pin 12.