Ook, answering my own post seems a bit silly, but I'm sure it can't hurt on the off-chance someone else is designing LCD controllers with CPLD's - more info the better eh?
I managed to get a test pattern up and running, but using a 'back porch' on the horizontal and vertical pulses. Essentailly, adding more pizels per line, and adding more lines. I know often these delays/extras are added by the controller to slow down the frame rate to fit into the 60-80Hz range when using different oscillators, but it seems that this LCD (and probably all) require it.
So, with a 320x240 Colour STN, there are 120 LCD writes per line (each write is a byte = 8*120 = 960, divided by 3 for 3-bits per pixel = 120), I'm writing 128. So thats 8 'dummy writes' at the end of each line. Also, I'm writing 244 lines - so thats 4 dummy lines.
With a burst of 4 reads from RAM, I then write a byte to the display. Another burst of 4 reads, leads to another LCD write. Finally, a delay period of 4 reads, then the last byte is written. Thats 8 RAM reads = 3 bytes written to display = 24 bits = 8 pixels. The gap between the second and third byte write to the display is used as a window to write to the ram, so one can write to the controller every 8 pixels. This is quite frequently meaning there is no need for a FIFO for incoming data, and a microcontroller would struggle to write any faster than this anyway. (every 3.6uS).
So far, looks like the entire thing will just about fit into an XC9572XL CPLD. I'm afraid 64-macrocell devices just aren't big enough, although would be fine for a monochrome 4-bit display up to 640x480. With the XC95144XL I'm using, I have room for a status register, config register, and the posibilty of display rotation (memory is arranged as 0-512 pixels/bytes per line, with 0-256 lines) - so one could just increment the 'line' part of the memory address, instead of the 'pixel' part, meaning the display is rotated 90 degree's.
Because of the distinct lack of examples on the web - ones that aren't designed to fit into a massive FPGA - I am hoping to put this up either in here, or on a website. My design isn't particularly special, although I'm quite pleased with myself that it fits into relatively small/cheap programmable logic devices
And if one already has the facility to work with CPLD's, its a hell of a lot cheaper than current LCD controllers. (S1D13700 is $9, SSD1906 is around $15, vs $3 for a 64 MC CPLD).
Next port of call is an actual screen photograph, then a full edsign for some Planar EL displays.
Apologies for using this forum as a 'platform' for my own blog-like rambling. But hopefully someone can get some use out of it.
Blueteeth.