Hi edeca,
Do the following steps for a neat schematic:
Grid size 0.025", size (letters) 0.056", ratio (standard 8) 6, layer95 (names). Click the symbol marked "ABC" (Label).
Next click the net you want to label and place the label at the selected position.
The bus "SOURCE[0..7]" is not only ugly, but unnecessary.
Buses make sense if many ICs on the board use the same signals, e.g. CLK, \CS, DATA[0..7] etc. Connect nets directly and label them properly instead.
When using buses you might label them as well to make reading of the schematic easy.
Boncuk