Controlled IMpedance PCBs

WHen designing PCBs for processors (like the COldfire 5485, 50MHz crystal, 200MHz speed) and FPGAs (like the Virtex 5 100MHz crystal, 500MHz speed), at what point are controlled impedance PCBs required? EXcept for the RAM between the processor/FPGA, external to the chips, the fastest data transfers will be 5MHz from a CMOS camera.

Did you say 5MHz? Do not worry. On the other hand, for video out to a connector and down 50 feet of coax to a monitor I would use 75 ohm traces.

Consider speed and trace length. For a FPGA next to a SRAM, I have run fast but my longest trace was well under 1 inch. My first “PC” (back before the word “PC”) was a ½ MIP Z-80 CPU where the data traces went across a large PCB, across a 10 connector back plain, to a memory board, across the memory board. Even at those slow speeds the 2 to 3 feet of traces required impedance matching and termination.

Where are you in Alberta? I lived in Hanna, Lacomb and "Rocky".

I live in Edmonton but have never heard of those places. (Somewhat similar to the US-Canada, East-West, or Toronto-Edmonton effect I guess). I don't leave the city too much.

I'm not too worried about the speed of the camera (although I had planned to serialize the data stream and send it down twisted pair to a deserializer in order to be able to have the camera on a longer cable. It's not a problem since I can find the right impedance twisted pair wire (just a bit hard to find it quantities of only a couple feet), but the connector and PCB traces that lead to the deserializer might be a problem. It's running at a speed of about 230.4Mbps.

The RAM speed itself is going to be 200MHz for the processor and 333MHz for the FPGA. How much do I need to worry about controlled impedances at these speeds? I think I need an 8-14 layer board anyways so it's expensive, but I don't know if additional cost for impedance control is neglible or not.

I mainly ask because the FPGA dev board has impedance control on it. But it's also much larger than my board would be. It's also making me worry a bit about the Coldfire and it's RAM, though not nearly as much.

Actually, if the camera is only spitting data out at 5MHz, do I even need 333MHz RAM on the FPGA? It already has distributed internal memory. I think I could probably use slower RAM or less banks to save money and make routing simpler.

Fpga & Ram

My brother lives in Edmonton.

Some FPGAs have serial differential inputs in a format that is like DVI video. Those traces must be “transmission lines”.
I changed the serial video into parallel inside the FPGA. That way the RAM worked at 25MHz.
I made a military targeting computer with a FPGA and memory. We processed 4 streams of video at one time. We used a ground layer, a power layer and 4 signal layers. (6 layers) I almost got it working on 4 layers.

ron@gradllc.com

It depends on the wavelength of the highest order harmonic in the signal. If the circuit dimensions start to approach an order of magnitude of 1/4 of a wavelength then you should start matching impedances.

It's normally best to count up to the 10th harmonic for a 50% duty cycle waveform and for pulses it's the same, it's 1/(shortest pulse)*10.

ronsimpson said:

My brother lives in Edmonton.

Some FPGAs have serial differential inputs in a format that is like DVI video. Those traces must be “transmission lines”.
I changed the serial video into parallel inside the FPGA. That way the RAM worked at 25MHz.
I made a military targeting computer with a FPGA and memory. We processed 4 streams of video at one time. We used a ground layer, a power layer and 4 signal layers. (6 layers) I almost got it working on 4 layers.

ron@gradllc.com

Click to expand...

How big were the FPGAs? I ask because I can get anything with up to 4 layers made pretty easily. Beyond that it starts to cost a fair amount (I think $600 was the estimate I got for a generic 4"x8" 12/14 layer controlled impedance PCB). When you say you almost got it to work with 4 layers, do you mean you weren't able to route it? Or do you mean that it failed when only 4 layers were used?

I'm just wondering why the dev board needed 14 layers and controlled impedance- whether it was for fanout or because high speed signals had to travel form one end to the other.

Also I need the logic inside the FPGAs a lot more than I need all those pins. Is there any harm in leaving those unused pins unconnected (like not fanning them out) and just disconnecting them during compilation? Or are there side-effects?

Altera EP1C4F32417.
When using ball grid arrays it takes many layers. You can only get at 2 rows of pads per layer. So if you have a 4 layer board and 2 layers for power/ground then there are only 2 signal layers. You can only get to 4 rows of pads. If you are very cleaver you can connect the memory and FPGA on 2 layers. It depends on board size. If things must be very tight then more layers are needed.

Most PCB designers play “connect the dots” while I change the design to make the layout work. If you put much more work into a good layout then the PCB will cost less.

Look at your compiler, it may leave the NC pins as output low.

ronsimpson said:

Altera EP1C4F32417.
When using ball grid arrays it takes many layers. You can only get at 2 rows of pads per layer. So if you have a 4 layer board and 2 layers for power/ground then there are only 2 signal layers. You can only get to 4 rows of pads. If you are very cleaver you can connect the memory and FPGA on 2 layers. It depends on board size. If things must be very tight then more layers are needed.

Most PCB designers play “connect the dots” while I change the design to make the layout work. If you put much more work into a good layout then the PCB will cost less.

Look at your compiler, it may leave the NC pins as output low.

Click to expand...

Right now it looks like an 8-layer board should do the job.
---Logic---
---GND---
---Logic---
---GND---
---PWR---
---Logic---
---GND---
---Logic---

Or a 6-layer board if I it turns out I'll only need to fan out the pins I need.
---Logic---
---GND---
---Logic---
---Logic---
---PWR---
---Logic---
except that I think the bottom logic layer is too far from the ground plane for my obsessive-compulsive liking. I'm still trying to decide whehter I should spent 2x the money to make sure everything works (buy buying the dev board) or to be very careful building it the first time around.

power & ground

>Or a 6-layer board if I it turns out I'll only need to fan >out the pins I need.
>---Logic---
>---GND---
>---Logic---
>---Logic---
>---PWR---
>---Logic---

The GND and PWR layers are AC ground. The two layers are heavily connected together with capacitors. Keep the PWR layer mostly copper and it makes a pretty good ground as far as A.C. is concerned. I would place the high speed serial data lines on Logic 1 or Logic 2 so it sees the real ground.

If you pin-out the FPGA right there will be only short lines that do not use VIAs, or only a very few feed thoughts.