Correct english term for alternative RS flip flop

[Grossel]

Hi all.

When searching on internet for RS latch, then no pictures similar to the one attached is shown. That make it obvious to me that the terminology for the type of latch is something else.

Anyone here that could put a name on it?

 

[alec_t]

The more usual term is "sr latch".

 

[MrAl]

Hi,


Another name is "Bistable Latch". It's usually drawn differently too, either a rectangle with S,R,Q,Q' or as two cross coupled NAND or NOR gates.

 

[Grossel]

Hi. It still puzles me that neither image search for "sr latch" or "Bistable Latch" return any circuit that is similat to the one I posted.

The thing about the circuit I attached is that the reset input will dominate and opposed to a regular sr latch, there is no actual ilegal input combinations.

 

[Ian Rogers]

The only thing I've seen resembling this circuit is a basic memory latch

This uses two NOR's rather than the AND and NOR.

 

[MrAl]

Hi all.

When searching on internet for RS latch, then no pictures similar to the one attached is shown. That make it obvious to me that the terminology for the type of latch is something else.

Anyone here that could put a name on it?

Hi,

I think you need to define your logic blocks better. There's no logic element that is >=1 just gates.

If you define the "&" gate as an AND gate then with zero output and both inputs zero, then letting S go to 1, there's no change on the output so you'll have to define the blocks better. The way it looks it doesnt work.

 

[KeepItSimpleStupid]

Sink your teeth into this: https://en.wikipedia.org/wiki/Flip-flop_(electronics) The two major types are the D- flip flop and the J-K flip flop.

The "D-FF" latches the contents on the transition of a clock pulse.

The JK FF has some interesting modes:
When J and K are both tied together, the outputs toggle on a clock pulse.
They can also behave like a D-FF, where J and or K is transferred on the clock pulse.
and there are separate S and R inputs to set the state of the latch.

 

[Grossel]

I think you need to define your logic blocks better. There's no logic element that is >=1 just gates.

Hi. A ">=1" gate means a OR gate. The european symbol. Takes less effort to draw manually.

The only thing I've seen resembling this circuit is a basic memory latch
This uses two NOR's rather than the AND and NOR.

Thanks. I agree this sound more like a reasonable term.

Still, searching for "basic memory latch" on the net still doesn't returns any images that looks like this schematic. I tried all the biggest search engines out there, and they all returned a lot of images of the well known SR flip flop (the one where upper and lower part is horisontally mirrored along the middle).

 

[KeepItSimpleStupid]

Still, searching for "basic memory latch" on the net still doesn't returns any images that looks like this schematic.

The Wikipedia article does. 1st pic on the right.

Does this help too: https://math.hws.edu/TMCM/java/labs/xLogicCircuitsLab2.html

 

[dougy83]

We call them RS flip flops here too.

There are a few depictions of circuits in the form you described, however most use the symmetric interlocked gates which have symmetric set/reset delays and no dominant state (thus an illegal input combination).

https://www.cs.princeton.edu/courses/archive/fall01/cs126/assignments/circuit.html
**broken link removed**
**broken link removed**

 

[MrAl]

Hi. A ">=1" gate means a OR gate. The european symbol. Takes less effort to draw manually.

Thanks. I agree this sound more like a reasonable term.

Still, searching for "basic memory latch" on the net still doesn't returns any images that looks like this schematic. I tried all the biggest search engines out there, and they all returned a lot of images of the well known SR flip flop (the one where upper and lower part is horisontally mirrored along the middle).

Hi,

Yeah, if ">=1" is an OR gate, then the circuit still doesnt work. Set both inputs low, the output goes to 1, which is ok so far. Then set R to 1 and the output goes low, which is still ok so far. Then return R to 0 and see the output go back to 0, which is not ok because it's not latching.

If you want to use AND and OR then i think you have to put the inverter maybe on one of the AND inputs instead of the OR input.

If you use two NOR gates you get an SR Latch and no inverter required. I you use two NAND gates also no inverter required and the two inputs are S'R' instead of SR. In either case where you take the output from affects the outcome to some extent as to which input has more control.

If you do a search on "Bistable Latch" or "Bistable Flip Flop" or "Bistable Multivibrator" it should turn up lots of hits.