counting a 24 pulse signal

[NeX]

hello,

i have a signal similar to sync24 used in music tempo syncing, and i want to count it so that every time the signal has gone high and back low 24 times it flashes an LED and resets the count.

now i have got as far as working out i might be able to use a 74160 synchronous decade counter coupled to a 74161 synchronous 4-bit counter, giving me the total 24,

but i am not sure if i am thinking in the right terms, is it right that once the binary counter has reached 15 i can get that to start the decimal counter going and then when that gets to 9 they trigger the LED and then both reset?

its for a BPM meter,

thanks everyone

 

[ericgibbs]

hello,

i have a signal similar to sync24 used in music tempo syncing, and i want to count it so that every time the signal has gone high and back low 24 times it flashes an LED and resets the count.

now i have got as far as working out i might be able to use a 74160 synchronous decade counter coupled to a 74161 synchronous 4-bit counter, giving me the total 24,

but i am not sure if i am thinking in the right terms, is it right that once the binary counter has reached 15 i can get that to start the decimal counter going and then when that gets to 9 they trigger the LED and then both reset?

its for a BPM meter,

thanks everyone

hi,
The 74160 is decade counter/divider [ 10's] the 74161 is a binary counter/divider.

You could clock the 74160 and use the 10th pulse to clock the 74161, four times.
Detect the falling edge of the 4th pulse and reset both counters.

Do you follow OK.?

 

[NeX]

hi,
The 74160 is decade counter/divider [ 10's] the 74161 is a binary counter/divider.

You could clock the 74160 and use the 10th pulse to clock the 74161, four times.
Detect the falling edge of the 4th pulse and reset both counters.

Do you follow OK.?

hi thanks for that, i thought the decade counter was 0 to 9?

and sorry i don't follow, that would give me 14 wouldn't it? i need every pulse to be counted so i can't count 24 pulses and then have the 25th clock transition do the reset because then it would be out of sync. eventually i would like the beats per minute to be read on an LED display.

 

[ericgibbs]

hi thanks for that, i thought the decade counter was 0 to 9?

and sorry i don't follow, that would give me 14 wouldn't it? i need every pulse to be counted so i can't count 24 pulses and then have the 25th clock transition do the reset because then it would be out of sync. eventually i would like the beats per minute to be read on an LED display.

hi,
0 to 9 is 10 steps..

Woops, its 14 as you say.

You would need to add decoding on the 74160 and 74161 so that on the back edge of 24 counts the counters are reset.

Do you already have these ic's on the shelf.???

 

[MikeMl]

This puts out a low ( and lights the LED) during the 24th clock cycle.

 

[NeX]

hi,
0 to 9 is 10 steps..

Woops, its 14 as you say.

You would need to add decoding on the 74160 and 74161 so that on the back edge of 24 counts the counters are reset.

Do you already have these ic's on the shelf.???

ok so 0-9 is 10 steps but does that mean the first clock pulse isn't counted? or comes up as "binary 0000" ?

no probs

by decoding do you mean having something like a NAND gate on the outputs that triggers the reset? does that mean there is no nice neat way of doing this with just the two chips? i am limited by space so the smaller i can make it the better, and cheaper obviously.

thanks for your help by the way

 

[NeX]

This puts out a low ( and lights the LED) during the 24th clock cycle.

hi there,

thanks very much for that diagram it looks perfect!

i am trying to use as few components as possible, or at least as small as possible, can the CD4011b NAND gates be used in a single IC? and the final CD4012b be made with transistors?

thanks again

 

[MikeMl]

There are two 4012s per package. There are four 4011s per package. If you can find a dual four-input AND gate instead of a NAND gate, then you could do it in two packages... One of the AND gates decodes Q4 and Q5 (state 24 or the counter), while the other decodes Q1,2,3, and Q5 (state 23 of the counter). You dont have to invert the clock. If using ANDs instead of NANDs, you dont have to invert the RESET signal... You will have to do something with the way the LED is driven.

 

[NeX]

There are two 4012s per package. There are four 4011s per package. If you can find a dual four-input AND gate instead of a NAND gate, then you could do it in two packages... One of the AND gates decodes Q4 and Q5 (state 24 or the counter), while the other decodes Q1,2,3, and Q5 (state 23 of the counter). You dont have to invert the clock. If using ANDs instead of NANDs, you dont have to invert the RESET signal... You will have to do something with the way the LED is driven.

thanks again for the help, i have found a 74ls21 which is a duel, four input AND gate.

so for the final output i would need a NOT gate to light the LED? unless i could be happy with the LED blinking off, instead of on?

this is great help,

sorry to do this but one last thing. if the clock stops (song is stopped) and then restarted (song is played again) the pulses will be out of sync because the counter has already counted from the previous clock input,

with the clock being low when the song is not playing, and being low for not more than a a few miliseconds whilst playing, is there any way to get the system to auto reset if the clock is low for too long?

i am sure this is doable with a capacitor in some way but i just can't think at the moment

thanks again!

 

[MikeMl]

I wouldn't mix 74LS with 4000 series CMOS. Look for a 4082 dual four-input NAND gate. Do you always want it to delay 23 counts after a pause in the clock (and light the LED during the 24th clock cycle? Which state will the clock stop in? On which clock edge do you want the counter to advance?

 

[NeX]

I wouldn't mix 74LS with 4000 series CMOS. Look for a 4082 dual four-input NAND gate. Do you always want it to delay 23 counts after a pause in the clock (and light the LED during the 24th clock cycle? Which state will the clock stop in? On which clock edge do you want the counter to advance?

ok 4082 it is then, any reason why not to mix them?

the clock pulses come in groups of 8, so one batch of 8 then a pause (low) and then another 8 then a pause and then another 8, that makes up one beat, and thats when i want the LED to light. on the 24th pulse. the pulses are tiny, so 60bpm will have the LED flashing once a second, meaning there are 24 pulses a second, but it is more likely that the bpm will be 120 or higher so 48 pulses per second.

the clock is low normally, it is only high to register the tempo, if there is no tempo (nothing playing) then the clock is low. the counter can advance on either the leading or falling edge it doesn't matter really, but out of good practice it might be better to have it on the leading edge to make it precise.

thanks again for your help with this!

 

[ericgibbs]

hi nex,
Mikes circuit looks OK, the only point I would make is that the 4024 is a 7 bit ripple counter, not synchronous.

The logic decode for the 24th count may have transition glitches as the 4024 counts up.
Depending upon the 'speed' of the circuit into which the 4024 is sending the 24th pulse into, these glitches could cause the receiving logic to malfunction.

The usual way to eliminate these switching glitches is by having a simple res/cap filter on the output of the logic 24th detection pulse logic. OK.?

 

[NeX]

hi nex,
Mikes circuit looks OK, the only point I would make is that the 4024 is a 7 bit ripple counter, not synchronous.

The logic decode for the 24th count may have transition glitches as the 4024 counts up.
Depending upon the 'speed' of the circuit into which the 4024 is sending the 24th pulse into, these glitches could cause the receiving logic to malfunction.

The usual way to eliminate these switching glitches is by having a simple res/cap filter on the output of the logic 24th detection pulse logic. OK.?

thanks, do you think that it might be easier with just a synchronous chip?

or is a capacitor going to be the easier option?

thanks for your help

 

[ericgibbs]

thanks, do you think that it might be easier with just a synchronous chip?

or is a capacitor going to be the easier option?

thanks for your help

hi,
I would use the 4024 and a res/cap filter.

 

[NeX]

hi,
I would use the 4024 and a res/cap filter.

ok cool, thanks for the tip. i have the parts on order so we will see what happens when they get here.

 

[MikeMl]

hi nex,
Mikes circuit looks OK, the only point I would make is that the 4024 is a 7 bit ripple counter, not synchronous.

The logic decode for the 24th count may have transition glitches as the 4024 counts up...

Eric,

If you look closely at the attached, I took this into consideration. The State24~ decode is glitchless and hazard-free because it decodes the first possible time that both Q5 and Q4 are High together as the counter advances 0,1,...,23,24 after a reset. I have been burned by glitches in decoding ripple counters before, and avoided it in this case...

Nex,

I went back to NAND gates for the 23 & 24 decode, and used two input NANDs to implement the "timer" which resets the counter whenever the clock stops. Look at the node labeled RC in the sim. You might have to play with the time constant a little bit to guarantee resets at all BPMs. You must use a CMOS quad two-input NAND gate to make the timing network work...

Contrary what it says on the schematic, the counter advances on the rising edge of clock...

 

[ericgibbs]

hi Mike,
Thanks for the update, I should have seen/realised that you would not have overlooked the possibility of transition glitches.

Regards.

 

[NeX]

Nex,

I went back to NAND gates for the 23 & 24 decode, and used two input NANDs to implement the "timer" which resets the counter whenever the clock stops. Look at the node labeled RC in the sim. You might have to play with the time constant a little bit to guarantee resets at all BPMs. You must use a CMOS quad two-input NAND gate to make the timing network work...

Contrary what it says on the schematic, the counter advances on the rising edge of clock...

thank you VERY VERY much for all this, this is great!

is it possible to have your email address so i can talk to you privately about this?

it looks perfect, i am assuming that the capacitor and resistor on the left are what is controlling the time out circuit, and i just adjust the ratios to suit my needs? the clock pauses shouldn't be more than 0.2 seconds maybe? on a very low BPM of something like 40 beats per minute, which is actually the lowest my system can handle anyway.

thanks again for this, i have ordered the components which are on there way, i am looking forward to seeing how this going to work. next job is to turn the BPM into a seven segment display read out! but that is later.

 

[MikeMl]

...

is it possible to have your email address so i can talk to you privately about this?

Use the Forum's own Private Message system. Since this is a "learning channel", it is better to post questions publically. That way, more folks can chime in, and more can learn from the discussion.

 

[Sceadwian]

If you want a specific users input just make it a forum thread and ask them to watch the thread in a private message. Once a poster has given advice on something they typically check back from time to time, but if you have a specific post you made you don't think someone read just PM them and point them back to the thread.