create a vhdl code from this mealy diagram

[cinderella1]

Hi, can anyone make a vhdl (using quartus software) from this mealy diagram?? i got the code already but there's no out put in my functional stimulation. The output is remain zero. Suppose, the output got 1 and 0 also. Thanks for helping

 

[edeca]

What code do you have already?

 

[cinderella1]

if u want to see the code, pm me

 

[fvm]

your logic is fine, i dont know abt the syntax of vhdl, i worked in verilog
you should check for syntax error, and sumtime running a program in new project help too
you didnt define the clk signal
for simulation you require a clk signal
start a loop for clk

 

[cinderella1]

soo???

What code do you have already?

 

[cinderella1]

thanks

your logic is fine, i dont know abt the syntax of vhdl, i worked in verilog
you should check for syntax error, and sumtime running a program in new project help too
you didnt define the clk signal
for simulation you require a clk signal
start a loop for clk

 

[Inquisitive]

We are all here to learn. If code for a given in a private message how are the people of the forum to learn? We learn from each other here.

If code is given in private only one or two people learn from the exchange. That defeats the purpose of questions on the forum.