Dear Nigel,
Most Design Engineers and Techs dont know that the Ciss * RdsOn product for a given family of Mosfets e.g. lithographic size is constant . Thus your RdsOn is too low causing Ciss to be too high eg >1000pf loading the input 33 pf cap in parallel and severely attenuating the Xtal feedback signal in parallel high impedance mode.
In CMOS gates, we call this simply parasitic junction capacitance which lowers the resonant frequency by as much as 25ppm say roughly, when the input is 5pF and the Xtal load capacitance is rated at 16 pF. But if you load it with 1000pF it attenuates the input more than the voltage gain of complementary MOSFETs. In unbuffered (UB) single stage CMOS gates had a gain from 10 old to 100 new for 74ALVC2xx types. Standard gates are 3 stages with a minimum gain of 1000 which can be too high for many crystals with overtones or harmonics.
Therefore, if the Ciss of the MOSFET was at least 100 to 1000x smaller and RdsOn was 100x bigger, it may have worked.
After about 10~20ms the input DC reaches V/2 and then the AC envelope grows according to inverse bandwidth where T= 1/2 * 1/f-3dB
Another factor is technology in last decades has made quartz crystals smaller , most that have been microsliced and have shrunk in volume orders of magnitude, which lowers the Q, quality factor or gain and rated load capacitance, so 33pF may not match your crystal, unless you have specs. It might only be 12 pF depending on supplier, thus two 24pf or a 27 out and 16pf input may be better, depending on circuit input capacitance.
I hope this makes sense to you. If in doubt, read then ask ! Ok?
Keep all 12MHz AC wires short (<1cm), and dont lose any hair. Then you can probe with short ground clip and feed 10cm without problems into logic over a ground plane or between to wide tracks with connections to a low inductance busbar ground on 1 layer, or twisted pair matched impedance or .. For greater lengths...