Damaging latch up in high side gate driver?

Hi,
We are doing a 2kW LLC half bridge with vout = 180vdc, vin = 400vdc, f(sw)~100kHz.

The hi side fet will be driven by having a hi side, 15v supply referred to the switching node. A gate driver will be powered by this and will drive the hi fet. The signal to this hi iside gate driver will be provided by either a NCP5181, or a 2ED2101S06F……

2ED2101S06F data

NCP5181 datasheet
https://www.onsemi.com/pdf/datasheet/ncp5106-d.pdf

Page 16 of the NCP5181 datasheet (above) warns of the problem of damaging latch up of the part if Vs spikes occur and go too low.
However, the 2ED2101S06F web page states that this latch up is not a problem..quoting them…

“Based on our SOI-Technology, the 2ED2101S06F has excellent ruggedness and noise immunity against
negative transient voltages on VS pin. With no parasitic thyristor structures present in the device, no parasitic
latch up can occur over all temperature and voltage conditions.”

So would you agree that the 2ED2101S06F is much more reliable? Is the NCP5181 a bit dodgy?

And, this is your hobby?

Mike.

Yes, The UCC21520 speaks of it, but just says it doesnt like 100V/ns+ between the said pins.
Ray Ridley speaks out against using bootstrap ics for offline PSU's at all, in his article "gate drive design tips"

I see that both parts are rated to 50V/nS. I am right up against 100V/nS and will not use these parts. They are good for most applications.
I think that both parts use a "level shifter" of the same kind and both do not like the Top Transistor going below ground. Maybe SOI has fixed the problem. I see they allow the top floating supply to go to -11 volts.

Thanks, also, the EDi family from infineon claims to be good to 150V/ns+...


...but its hard to tell if it would be less robust than an actual gate drive transformer....although the EDi family seems to actually be a "core-less" gate drive transformer....so surely it should not suffer at all from negative voltage spikes on the bridge switching node?