I'm a bit confused about something in DDR RAM. There appears to be clock pins and DQS pins but they seem to do the same thing right now. RIght now, my understanding is that the rising/falling edges of the DQS signal is used to "sync data to the external clock". My interpretation of that is that this is so the RAM knows when to capture data being written to it, and the processor knows when to capture the data being read from the RAM. But...wouldn't that just mean DQS is the clock itself? It's obviously not, so what am I missing here? Why wouldn't you just sync data in and out with the edges of the clock itself? Why do you need another signal to do it? Seems a rather redundant and roudabout way to do things right now from where I'm standing.
And a side question- that data mask is just simply to write data to the RAM without changing certain bits right? To save cycles otherwise you would need to read it out of the RAM chip, record the value of the bits to be masked, only to rewrite them back to memory along with the modified bits?
And a side question- that data mask is just simply to write data to the RAM without changing certain bits right? To save cycles otherwise you would need to read it out of the RAM chip, record the value of the bits to be masked, only to rewrite them back to memory along with the modified bits?
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