Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
picasm said:It depends on the clock frequency and it takes 4 clock cycles per instruction cycle on 16F range chips.
Eg. a 4Mhz clock takes 1uS per instruction cycle.
Most instructions use one cycle - but a few sometimes use 2 such as conditional instructions eg. DECFSZ.
For precise timing loops there is a useful generator provided by the "piclist" at:
Alternatively, you could use one of the counters - they are very accurate and can be set to interrupt when the desired delay has been reached.
eng1 said:You can count the overflows of TIMER0. Since it is a 8 bit register, it counts up to 255, then it overflows and an interrupt occurs. Then it starts from 0 again.
Interrupts must be enabled with the INTCON register of course.
TIMER0 will overflow x / 256 times per second, where x depends on the frequency of your clock.
This isn't my area but itsn't that 250nS, if each instruction takes one cycle.picasm said:Eg. a 4Mhz clock takes 1uS per instruction cycle.
Most instructions use one cycle
eng1 said:You can count the overflows of TIMER0. Since it is a 8 bit register, it counts up to 255, then it overflows and an interrupt occurs. Then it starts from 0 again.
Interrupts must be enabled with the INTCON register of course.
TIMER0 will overflow x / 256 times per second, where x depends on the frequency of your clock.