Delta sigma ADC circuit verification.

[Lightium]

Hello everyone,

Can anyone tell me how is this a delta sigma ADC? I have never studied digital circuitry, so any help is great and much appreciated.

 

[Diver300]

As I understand it, the op-amp U1B controls its average output voltage so that the two inputs are at the same voltage. That is in a similar way that it would if R202 were directly in parallel with C201. The comparator and latch mean that the output is either high or low, and can only change when the clock pulse occurs, but that doesn't change the fact that the average voltage on pin 5 of U3A has to make the average voltage on the inverting input of U1B equal to the voltage on the non-inverting input.

If the input voltage is in the middle, and equal to refh (2.5 V), pin 5 of U3A also has to average 2.5 V so it will be high for one clock cycle and low for one clock cycle.

If the input voltage is low, pin 5 of U3A has to be high most of the time, so there will only be the occasional low clock cycle.

The digital output is from pin 6 which is inverted from pin 5, so pin 6 will be low most of the time when the input is low.

The A2D is completed by getting the digital circuit wait for clock cycles on U3B. At each clock cycle, count up if the output of U3A is high. After enough clock cycles on U3B, the total of the times high on U3A is the voltage.

e.g, if after 10 clock cycles on U3B, the output of U3A was high during 3 of those, (so low during 7 of them) then the voltage is at 30% of the input range.

I think it's common to wait for at least 100 counts on U3B.