shift registers won't increment, so you'll also need some kind of counter; but you can use a serial to parallel shift register (plus xor gates) to create a sequencer. Also, there is no "Address Latch Enable" to tell when you have a valid address/r/w command (or enable, or start command input).
So, here are the commands you'll need to generate:
Read: 1) disable output oe 2) enable memory output enable (oe) 3) latch data to output register 4) disable memory oe, enable output oe 5) issue end cmd (reset start f/f)
Write: 1) disable output oe (last command could've been read) 2) enable mem oe, enable buffer 1 oe (memory to counter register) 3) latch data into ctr register 4) disable mem oe, buff1 oe, inc ctr 5) enable buffer 2 oe (ctr to memory) 6) enable memory write 7) disable memory write 8) disable buffer 2 oe 9) issue end cmd (reset start f/f)
The above command sequence assumes:
1) the memory is cs enabled all the time (chip select).
2) you only output on a read command.
3) separate ctr/output buffers. These can, of course, be combined into one.
4) Uses output buffer register so output doesn't change as memory address changes, until start command.