DFF VLSI operation when t=0

I have done a VLSI Design Layout Simulation of a D Flip-Flop. The timing diagram and schematic are as attached.

The simulation works fine and the results as desired. However I noticed, that at the timing diagram, when t=0, there seems to be a slight peaking at the output of Q' and a charge up at Q [indicated on the attached picture].

Why is this so?

I think it is an initial power up "race" condition where the cross-coupled E and F gates are both initially low at power-up, which feeds back to the inputs of E and F, but clearly, both cant be low nor both can be high at the same time, so due to a slight imbalance one wins. If you were using a "logic" simulator, both E and F would initially have a value of "unknown". If you are using a Spice sim, use the .IC statement to set one or the other to an initial state other than the default low, and see what happens.

hey..that makes perfect sense! thank youu so much!=)