I'm trying to clarify something.
In a mosfet, it is bad for Vds to rise too quickly; this is what the dv/dt parameter is for. In this particular case I'm looking at this mosfet https://www.st.com/stonline/stappl/productcatalog/app?path=/comp/stcom/PcStComOnLineQuery.showresult&querytype=type=product$$view=table$$orderable=yes&querycriteria=RNP139=1167$$rpncode=220805 which has a dv/dt of 45V/ns. However, when you apply your main power to your circuit, is it just the intrinsic impedance of the circuit that usually prevents it from rising too fast?
I'm sure the input capacitance, snubber capacitance, etc would decrease the dv/dt. But is that all? Am I missing something?
In a mosfet, it is bad for Vds to rise too quickly; this is what the dv/dt parameter is for. In this particular case I'm looking at this mosfet https://www.st.com/stonline/stappl/productcatalog/app?path=/comp/stcom/PcStComOnLineQuery.showresult&querytype=type=product$$view=table$$orderable=yes&querycriteria=RNP139=1167$$rpncode=220805 which has a dv/dt of 45V/ns. However, when you apply your main power to your circuit, is it just the intrinsic impedance of the circuit that usually prevents it from rising too fast?
I'm sure the input capacitance, snubber capacitance, etc would decrease the dv/dt. But is that all? Am I missing something?
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