It is a two-stage process resulting in ten bits being used to represent eight bits. In the first stage each bit is either XOR or XNOR transformed against the previous bit, whilst the first bit is not transformed at all. The encoder chooses between XOR and XNOR by determining which will result in the fewest transitions; the ninth bit is added to show which was used. In the second stage, the first eight bits are optionally inverted to even out the balance of ones and zeros and therefore the sustained average DC level. The tenth bit is added to indicate whether this inversion took place.