The clocking, which is the SLD line, is controlled by the master.
I can program it in such a way that one high pulse width is, say, 5us, and the following pulse is 6us.
It doesnt really matter.
The datasheet state the maximum or minumum timing requirement. However, it is not always accurate.
I have written a prorgam that works fine with a 64K Atmel EEPROM, AT24C64. However, it failed to read/write 512K EEPROM, AT24C512, despite both timing diagram are almost identical as stated in datasheet.
So, I just added some delay, and it runs perfectly.