I'm confused...
**broken link removed**
"Optimal placement of ESD suppressors begins at the location of ESD penetration into the system. This tactic reduces the ESD voltage and current initially experienced by the circuit and attenuates the ESD pulse that propagates past the ESD suppressor. Design as much practical space as possible between the ESD suppressor and the protected chip.
Placing an ESD suppressor too far away from the line it's protecting can reduce its effectiveness. The board trace inductance can cause an additional amount of voltage, or "overshoot," on the chip. To avoid this, install the ESD suppressor as close to the protected line as possible
"
Don't these statements conflict? Or am I misinterpreting the wording?
**broken link removed**
"Optimal placement of ESD suppressors begins at the location of ESD penetration into the system. This tactic reduces the ESD voltage and current initially experienced by the circuit and attenuates the ESD pulse that propagates past the ESD suppressor. Design as much practical space as possible between the ESD suppressor and the protected chip.
Placing an ESD suppressor too far away from the line it's protecting can reduce its effectiveness. The board trace inductance can cause an additional amount of voltage, or "overshoot," on the chip. To avoid this, install the ESD suppressor as close to the protected line as possible
"
Don't these statements conflict? Or am I misinterpreting the wording?